Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
EE Times-Asia > Networks

Cadence platform accelerates interconnect design

Posted: 11 Mar 2004 ?? ?Print Version ?Bookmark and Share

Keywords:cadence design systems? allegro? interconnect design platform? virtuoso? encounter?

The Allegro system interconnect design platform from Cadence Design Systems Inc. is designed to accelerate high-performance, high-density interconnect design.

Lavi Lev, EVP and GM, said, "The Allegro platform provides an optimized, high-performance solution to that problem that delivers significant time and cost savings."

"Combined with the Cadence Virtuoso and Encounter platforms, Allegro enables customers in the semiconductor and systems space to overcome the inherent challenges of design chain collaboration and high-speed system interconnect design," he added.

System interconnect

The new platform provides a common constraint-driven flow across design entry, signal and power integrity, and addresses the implementation of system interconnects. It supports a co-design methodology that provides for the design, modeling, and analysis of the system interconnect across all three fabrics.

The methodology takes the system interconnect from specification through exploration, design, implementation, verification, manufacture, and correlation.

The term "system interconnect" refers to the logical, physical, and electrical connection of a signal, its associated return path, and power delivery system. It travels between different IC I/O buffers and traverses die bump pads, package substrates, connectors, and PCBs. Cadence explains that design and analysis of the system interconnect is often performed using a highly-fragmented set of design processes across three different fabrics - IC, IC packaging, and PCB.

At the core of this methodology is a virtual system interconnect (VSIC) model that is used to capture the original design intent and is matured throughout the design process as various segments of the interconnect are implemented. Through the VSIC model, engineers can design and implement their portion of the system interconnect within the context of the whole.

The platform also includes a common constraint management system integrated across hierarchical schematic capture, high-speed design and analysis, and IC package and PCB layout systems.

Article Comments - Cadence platform accelerates interco...
*? You can enter [0] more charecters.
*Verify code:


Visit Asia Webinars to learn about the latest in technology and get practical design tips.

Back to Top