Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
EE Times-Asia > EDA/IP

Agere employs Cadence RTL compiler synthesis

Posted: 12 Mar 2004 ?? ?Print Version ?Bookmark and Share

Keywords:agere systems? cadence design systems? encounter rtl? compiler synthesis? asic?

Agere Systems is accepting netlists produced by Cadence Design Systems Inc.'s Encounter RTL compiler synthesis for implementation in its ASIC design centers.

Used throughout the silicon design chain by IP vendors, IC, and ASIC designers, Encounter RTL Compiler synthesis works to increase overall chip speed, reduce turnaround time, and help customers achieve the highest quality of silicon (QoS), claims Cadence. The Encounter RTL Compiler synthesis is a key component of the Encounter digital IC design platform and a critical step in the fastest route to superior silicon, adds the company.

"Getting faster chip speed with smaller die size in less time is valuable to every design team. The superior RTL Compiler results on our high-density gigabit Ethernet switch, gave us a much shorter timing closure process than we expected," said Shankar Mukherjee, director of Ethernet switch development at Agere. "Having more margin on this complex multi-million-gate IC before place and route made our ASIC handoff much smoother," Mukherjee added.

Article Comments - Agere employs Cadence RTL compiler s...
*? You can enter [0] more charecters.
*Verify code:


Visit Asia Webinars to learn about the latest in technology and get practical design tips.

Back to Top