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Engineer offers free obfuscator, layout scanner

Posted: 15 Mar 2004 ?? ?Print Version ?Bookmark and Share

Keywords:e-mail synopsys users group? verilog source-code obfuscator? rtl?

Inspired by a user request in the E-Mail Synopsys Users Group (ESNUG), an engineer working in Singapore developed a Verilog source-code obfuscator, a GDSII layout viewer, and a layout scanner that calculates wire length. All are available for free downloading from Eng Han Lee's web site.

Lee currently works at Future Technology Designs, a company involved in design services and intellectual property (IP) development. His current responsibilities include placement and routing. The tools at his EDA Utilities web site were developed in his spare time.

Lee said he developed VO, the Verilog obfuscator, during a "two month break" before joining Future Technology Designs. He was inspired to do so by a user request for an obfuscator in a 2000 ESNUG bulletin.

Obfuscators are used to render Verilog code unreadable for security purposes. VO reads in RTL or gate-level Verilog, and generates obfuscated names. Users can specify the names, preserve what's there, or let the tool produce them. It provides a cross-reference of original and obfuscated names, and provides verification for the obfuscated output.

"It is written for [Verilog] 1995, with some 2001 syntax," Lee said. "I have a plan to make it support 2001, but lack the time to make this come true."

Lee went on to create lv, a GDSII layout viewer that reads GDSII files and provides graphical views. It supports zooming and panning, layer selection, and a grid display, and produces a layout summary report.

Finally, edaUtils-Is is a layout "scanner" that identifies long interconnects in the layout of a routed design. "The basic idea is to have a set of utilities that scan a digital design layout for potential issues," Lee said. "The first attempt is to report long interconnect routing."

edaUtils-Is calculates the wire length from an input to an output. The result is compared with the shortest possible interconnect, and if the ratio exceeds a user-defined threshold, the interconnect is reported as "long." As such, the tool provides a score that can identify areas that need improvement, or help users benchmark between two placement and routing engines.

The current implementation supports Synopsys Apollo layout tools only. Lee said he is hoping to find time to add support for Magma Design Automation. The utility does not support hierarchical layout.

All of these tools are available "as is" for free download. "Support is in between my free time," Lee said. He noted that there have been over 1,000 downloads in the past three years.

Lee plans to add more tools in the future. "For example, I want to develop a tool to display the clock tree in a way that place and route engineers want to see," he said.

Richard Goering

EE Times

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