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Passive integration activates wireless

Posted: 16 Mar 2004 ?? ?Print Version ?Bookmark and Share

Keywords:passive integration? rf cmos? cmos? bicmos? wireless?

The wireless-design community has placed increased pressure on CMOS and BiCMOS foundries to combine multiplatform design environments into a single one to support silicon and packaging co-design. Advanced silicon processes, like SiGe, BiCMOS and RF CMOS, are migrating from generic design kits of the past to fully customized kits with "hooks" reaching outside the traditional design environment. For example, design kits are starting to include sophisticated electromagnetic simulators or resistive-inductive-capacitive lumped-element extraction engines that provide higher accuracy than a simple RC-equivalent circuit model. These custom tools are being incorporated into the silicon and package design flow, giving designers the flexibility of an easy-to-use complete system-in-package (SiP) solution.

Understanding the influence and impact the package has on silicon circuits, and working that back into the design flow, can be extremely time-consuming. The parasitic reactance associated with the package interface and interconnect can seriously degrade the performance of the silicon circuit. Thus, integrating an EDA tool into a foundry design kit that extracts accurate models will enhance the designer's ability to create, simulate and optimize both on-chip and in-package passives, including inductors, baluns and transmission lines.

The passives-integrated-in-package (PiiP) concept is a unique design approach for integrating package-level design into the silicon world via Atmel's present 0.35m BiCMOS SiGe process. It provides a single design platform for co-simulating both package-level and silicon passives models within Cadence Design Systems Inc.'s design environment.

The platform, designated Helmet, was introduced in 1999 by Atmel and Helic SA to support Atmel's on-chip inductor program. Helmet was immediately integrated into the in-package inductor-generation program using a low-temperature co-fired ceramic (LTCC) substrate as the package.

The Helmet software currently supports in-package structures, including single-ended and differential inductors, transmission lines and stacked capacitors embedded within the LTCC substrate, with several other substrates currently being evaluated (low-k and high-resistive).

Inductor-modeling engine

Helmet's inductor-modeling engine is powered by a set of proprietary algorithms, adapted by Helic for Atmel's PiiP and SiGe BiCMOS processes. The modeling engine can rapidly produce accurate spiral inductor, transformer and RF interconnect models, taking into account mutual inductance effects. Its speed significantly outperforms conventional electromagnetic simulators, making it ideal for the extraction of large-scale RF IC designs incorporating silicon and in-package passives.

The tool supports RLCk (resistive-inductive-capacitive-mutual-coupling coefficient) netlists, making it compatible with any SPICE-type circuit simulator. Atmel has tested Helmet simulation models extensively against measured devices, establishing their accuracy with several metallization options. For spiral inductors, the prediction of inductance, quality factor and self-resonance frequency is accurate within 5 percent.

The design of package substrates has traditionally been carried out with PCB design tools completely detached from the IC design flow. This method has now been rendered obsolete with the increased levels of chip-package integration brought about by PiiP. In advanced RF module development, it becomes more "natural" for the RF IC design group to handle package design as well.

For Helmet, Atmel and Helic developed a unified design flow for chip and package co-design based on Cadence's Virtuoso platform. Coupled with the tool's powerful passives extraction capabilities, this design flow has the advantage of a seamless physical design and simulation interface among on-chip and in-package devices. Helmet makes it possible to extract and simulate a complete SiP from a merged layout view in a single step. Data transfers between different EDA environments are avoided and the design process is greatly accelerated and free from errors.

The passives generation tool is contained within the layout environment, which offers an advantage when creating and optimizing layout-driven devices like metal interconnects and inductors. Various inductor geometries, including circular, rectangular, octagonal and irregular, are supported and differential geometries are now being evaluated in silicon and other substrates for future integration into the environment. A pull-down menu has been included to make vendor selection, spiral p-cell generation, model extraction and model verification over frequency extremely user-friendly.


Automatic model extraction includes a typical fast and slow Spectre and HSPICE model. However, a compact model is also generated, offering a trade-off between accuracy and simulation speed.

The tool is also fully integrated into the Cadence back-end verification flow: design rule checking and layout-vs.-schematic. Finally, two-port Cadence symbolic views are generated for use in design schematics.

Atmel and Helic developed demonstrator PiiP modules incorporating Atmel silicon and LTCC substrate passives. Using Helmet, a linear passive mixer BGA was designed. The LTCC substrate hosted balun transformers, inductors and capacitors for impedance matching and RF, IF and LO port interconnects. The design worked on first pass, validating the design flow and establishing Helmet's accuracy in a true RF SiP environment.

A single design platform, Helmet, co-simulates package-level passives models and silicon passives models within Cadence's design environment.

Helmet software supports single-ended and differential inductors, transmission lines and stacked capacitors.

- Ron Wood, Sotiris Bantas

Atmel Corp., Helic SA

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