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Synthesis methods for ASIC, FPGA designs

Posted: 16 Mar 2004 ?? ?Print Version ?Bookmark and Share

Keywords:fpga? asic? ip? eda? soc?

Amazingly, Moore's Law continues to hold true. Despite predictions of unfathomable hurdles at each juncture in technological evolution, ASIC and FPGA densities continue to double approximately every 18 months as predicted by Intel's Gordon Moore years ago. In fact, by witnessing the continuation of a longstanding trend of integrating more functionality on a single IC, some believe that the pace of this progression may be accelerating. SoCs containing logic, memory, processors and mixed-signal elements are common today, while embedded FPGA and analog elements are on the horizon.

Moreover, with underlying silicon technology on par, the SoC designer today has many choices across the spectrum of ASIC and programmable logic solutions--meaning that the issues driven by SoC complexity are being seen in both ASIC and programmable logic design flows.

As those of us in the design community have learned, the meteoric rise in silicon potential is a mixed blessing. On one hand, we have silicon technology that delivers functionality and performance capabilities to meet the demands of even the most competitive applications. On the other hand, we have frustration with design tools that limit our ability to realize the full potential of this silicon technology. Sheer design size and device complexity make the design task now the limiting factor in the types of ICs that can be realized today. This so-called "productivity gap" continues to widen despite the near-myopic focus of the EDA community in recent years.

The synthesis challenge

Nowhere is the productivity gap more evident than in the area of synthesis. Processing capacity limitations of conventional synthesis approaches demand that designs be partitioned into sub-blocks of no more than 200,000 gates. With current silicon capacity of up to 20 million gates, designers conceivably would need to manage 100 or more different sub-blocks to synthesize a design.

In addition, partitioning based on gate count is non-intuitive for most designers who are more comfortable with partitioning based on functionality or timing. Another failing of current synthesis flows is that they do not separately optimize discrete functions well. This is exemplified by the demand for separate datapath synthesis today. Embedded FPGA will require both specialized synthesis mappers and optimization in context of the full chip.

Given the staggering increase in design complexity over the years, it is really no surprise that the efficacy of conventional solutions is waning.

Design complexity creates a number of other problems for synthesis technology. Memory utilization becomes a real challenge when a sophisticated synthesis application must actively operate on a large volume of design data. Runtime gets protracted not only by the sheer size of a design, but also by design management overhead required to handle the computational task. IP integration presents challenges as highly complex and constrained functions that must be factored into the synthesis process. Design cycles increase dramatically on complex designs, with iterations to reconcile timing issues or interblock dependencies lengthening design time.

Another significant challenge for synthesis solutions when applied to complex designs is that of maintaining stability, a term that refers in synthesis to the extent to which incremental changes to a design have ripple effects. Incremental synthesis, whereby only portions of a design are refined, can create complications when refined sub-blocks are incorporated back into the whole. These complications occur at an increasing rate as designs, and the underlying silicon technology, become more complex.

Common incremental approaches that fail to adequately account for the behavior of elements external to the sub-block being modified, or the interaction between the sub-block and the remainder of the design, can create chaos late in the design cycle. Incremental synthesis can also make formal verification difficult if changes impact multiple parts of the design.

To avoid the shortcomings of synthesis tools, designers are deploying several alternative strategies. One is complex workarounds such as sophisticated scripting. These elaborate and clever workaround solutions can achieve the end, but often unduly compromise quality of results (QoR) and productivity. Extensive manual scripting is often required to successfully synthesize a large ASIC design using conventional approaches, but the manual nature of such scripting makes it error prone, and demands designers to be highly skilled in scripting techniques. This effort also does little to "add value" to a design, consuming valuable manpower and time that could otherwise be employed to improve design results. Undermining these scripting efforts is that the gate count of the scripted partitions must fit within the memory capacity of the synthesis tool.

Yet another strategy is to focus strictly on RTL design and handoff RTL to an ASIC vendor for synthesis and implementation. Thus, the designer avoids the tedium associated with conventional synthesis by delegating it to the silicon vendor. This "RTL sign-off" approach is highly dependent upon intelligent, high-quality RTL and the willingness of vendors to shoulder the responsibility for design results. Designers also may be concerned about passing off a design to someone who is less knowledgeable about design and system issues, and is less vested in the success of the design.

These strategies, by their very nature, assume that synthesis cannot be improved or made less of a bottleneck. However, synthesis is an integral and essential aspect of all advanced IC design flows. To allow this technology to continue to create difficulties in implementation compromises the productivity and quality of the design effort, regardless of who performs synthesis. Thus, the synthesis problem is one that must be addressed.

Top-down vs. bottom-up

Traditionally, there have been two ways to attack the synthesis problem: bottom-up and top-down. Each affords some benefits and drawbacks. The bottom-up approach refers to partitioning a design into blocks that are within the capacity of the synthesis tools. By breaking up a design into pieces, each element can be processed independently and as required by changes to that part of the design. This allows for partial recompilation and multiprocessing that will speed up design compilation. A bottom-up flow also makes it possible to isolate parts of a design for incremental improvement independent of the rest of the design. If employed correctly, this can improve stability of results.

The bottom-up approach offers the best runtime on a per block basis, though overall runtime may suffer because of the project management and manual scripting overhead. The scripting effort alone can be significant, and is prone to error. There is also a QoR penalty with this approach. With a bottom-up approach, the synthesis tool can only "see" optimization opportunities within the partition, not across partition boundaries. This can eliminate the possibility for significant overall design improvements that span multiple partitions. As the number of boundaries increases, a design is further away from the best possible QoR. With two blocks, you miss some optimization opportunities--with 100 blocks, you miss many, many more.

The top-down approach to synthesis takes the entire system-level RTL and constraints, and allows the synthesis tool to optimize and bring the design to the gate level in one operation, without operating across partitions. When compared to a bottom-up design, this approach produces the best QoR because the synthesis tool is operating on the entire design. It is also easier to implement because the need for manual scripting is eliminated, as well as the need to manage the various partitions.

However, memory and runtime requirements are prohibitive for large designs. Design iterations require that the entire design be resynthesized for even minor changes, and are thus almost impractical except for very small designs. Likewise, replicated blocks run top-down will be individually synthesized, causing a longer runtime than the bottom-up approach of synthesizing the replicated block once, then "copying" it multiple times as the final top-level integration takes place.

Finally, the place-and-route process can be greatly streamlined, and iterations to meet timing closure can be avoided if a design is synthesized hierarchically with the same blocks. The top-down approach is ideal in terms of delay QoR, but to accommodate other design needs or sizes may not be the best for every design.

Neither a purely top-down nor bottom-up synthesis approach is the right answer for many designs. Instead, what is needed is an approach that combines the ease of use and QoR of top-down, with the productivity and lower memory requirements of bottom-up. This is particularly important in the case of large designs, where existing top-down or bottom-up only flows prevent optimal QoR and runtime.

Economics and market forces compel us to deploy the best that silicon technology has to offer. With synthesis, engineers can use an advanced, high capacity, highly automated design flow for both FPGA and ASIC designs. Capabilities such as difference-based incremental synthesis, automatic ILM creation and use, and user-definable compile points make this flow more attractive for designing large ASICs and FPGAs than any other approach. It embodies a unique mix of traditional top-down and bottom-up synthesis approaches and advanced synthesis techniques that enable high QoR and productivity when developing today's highly complex SoCs and PSoCs.

Figure 1: Design complexity continues to double approximately every 18 months despite the fact that conventional design flows are unable to keep pace.

Figure 2: With today's complex ICs, the only way to ensure both productivity and QoR is to use a different approach, combining the QoR of top-down synthesis with the stability and productivity of bottom-up synthesis.

- John Gallagher

Synplicity Inc.





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