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Synopsys takes another stab at FPGA synthesis

Posted: 18 Mar 2004 ?? ?Print Version ?Bookmark and Share

Keywords:fpga synthesis? synopsys? design compiler asic synthesis tool? asic? fpga?

Making its fourth run at FPGA synthesis, Synopsys Inc. has tweaked its Design Compiler ASIC synthesis tool to enable designers to use the same tools and potentially the same design flow for ASICs and FPGAs. The $19,600 add-on will be announced this week.

The product lets Design Compiler implement ASIC designs in FPGA devices without changing RTL code, synthesis constraints, scripts or ASIC IP.

Synopsys dominated the ASIC synthesis tools market last year with a 90 percent share despite stepped-up competition from Cadence, Magma, and Synplicity, according to Gartner Dataquest. But it takes a back seat in FPGA synthesis to Synplicity and Mentor Graphics, which respectively held 44 percent and 43 percent market shares in 2003, Gartner Dataquest said.

Now Synopsys wants to leverage its position in ASIC synthesis to once again pursue the FPGA synthesis market, specifically FPGA-based ASIC prototyping, where Synplicity Inc.'s Certify technology holds sway.

Gal Hasson, director of marketing for RTL synthesis at Synopsys, said that 40 percent of the company's customers in a recent survey reported they prototype their ASIC designs in FPGAs. "That's up from last year," said Hasson; only 20 percent of users surveyed in 2003 said they prototyped ASIC designs in FPGAs.

There are several reasons for the increase, said Greg Tanaka, group marketing manager for FPGA synthesis at Synopsys. High-end FPGAs have roughly the same number of gates as midsized ASICs. Designs programmed into high-end FPGAs typically run faster than those prototyped in emulation systems, and FPGA-based prototyping is cheaper than emulation.

Companies conducting ASIC designs are also finding more uses for FPGA prototypes, Hasson said. The prototypes are being used as an alternative to emulation for in-system verification, they give software engineers a jump on development and they can prove a concept when pitching new functionality to customers or management, Hasson said.

To capture this growing market for FPGA prototyping and reenter the FPGA synthesis market, Synopsys has created Design Compiler FPGA, calling it a marked shift from current procedures.

"Prototyping today is like designing another chip," Hasson said. Designers traditionally use an ASIC synthesis tool to complete an ASIC design, then use a separate FPGA synthesis tool to implement the ASIC prototype in an FPGA.

The switch from one synthesis tool to another requires many changes to code and scripts, is time-consuming and raises the potential for introducing errors into the prototype that do not accurately reflect the functionality of the ASIC design, Hasson said. Design Compiler FPGA will allow designers to use the familiar Design Compiler flow for ASICs to implement FPGAs, he said.

The tool also includes a feature called Adaptive Optimization that implements a design in FPGAs that, on average, is 15 percent faster than those implemented in competing FPGA synthesis and ASIC prototyping tools.

Adaptive Optimization will analyze a design and FPGA architecture and indicate the best algorithms based on that information, said Hasson. Then it dynamically tunes and reorders the algorithms to plot the fastest/shortest paths on an FPGA.

Because the new offering basically adds FPGA synthesis to Design Compiler, FPGA designers can easily use other ASIC tools in the FPGA design flow, such as Synopsys' PrimeTime for static timing, Formality for formal verification and Leda for linting, as well as DesignWare libraries.

FPGA designers have traditionally been unwilling to pay ASIC prices for tools, having grown accustomed to using tools that FPGA vendors provide at little or no cost. But Hasson said that FPGA tools require more sophistication, ASIC-like design capabilities and verification flows as FPGAs reach into the millions of gates. Established tools and design flows already exist in the ASIC design flow to address that complexity, he said.

While FPGA vendors offer increasingly sophisticated tools, they do not provide ASIC prototyping tools, Hasson said.

Synplicity jumped into the ASIC prototyping market with Certify, which has met with moderate success from ASIC designers, Synplicity said. A one-year license for Certify costs $45,000, and a perpetual license costs $115,000.

Synopsys' pricing for Design Compiler FPGA starts at $29,000. Synopsys said it is not only going after Synplicity's FPGA prototyping product, but against the FPGA synthesis marketplace.

Design Compiler FPGA, which includes Design Compiler plus the FPGA synthesis add-on, starts at $36,750 for a one-year standalone technology subscription license. Existing Design Compiler users can purchase the add-on for $19,600 for a one-year technology subscription license.

Earlier FPGA synthesis efforts by Synopsys failed. It introduced FPGA Compiler in 1992, the Windows-based FPGA Express in 1996 and FPGA Compiler II in the late 1990s, but those tools did not grab significant business from Synplicity or Exemplar Logic (Mentor Graphics acquired Exemplar in 1999). FPGA Express is now defunct; Synopsys still sells FPGA Compiler II, but for smaller FPGAs.

Select Synopsys customers have beta tested Design Compiler FPGA and put the technology through its paces, successfully completing prototypes, Hasson said. The company has signed 40 customers for Design Compiler FPGA, including Advanced Micro Devices, Agere Systems, Harris, and Texas Instruments, he said.

- Mike Santarini

EE Times

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