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Optical switch benefits from off-chip drive

Posted: 01 Apr 2004 ?? ?Print Version ?Bookmark and Share

Keywords:optical switch? b-pwm? pwm? d-wdm? mems?

D-WDM networks require transparent switches and optical add-drop multiplexers that are compact, cost-effective and remotely reconfigurable. Products based on MEMS are attractive because of low-cost batch processing, uniformity and good optical performance.

As more electrostatic MEMS-based optical-switch products penetrate the market, three figures of merit take on increased significance: scalability, reliability and tilt precision.

Past efforts toward achieving these goals have focused on the MEMS device itself, but real-world applications show that the drive electronics and packaging surrounding the MEMS play an equally important role. Movaz Networks has demonstrated a drive chip set for dense-array electrostatic MEMS that provides advantages over conventional solutions.

A commonly used drive implementation segregates the amplifier/driver from the tilting micromachined mirror. Each electrode on the mirror array chip is typically wire-bonded to a PCB. On the PCB, a high-voltage op amp, fed by a D/A channel, supplies each voltage. Several off-the-shelf high-voltage op amp ICs have been developed specifically for this implementation.

The MEMS micromirror itself is a flat plate, made of a conductive material suspended above a cavity on hinges. Two electrodes, called North and South, are patterned into the floor of the cavity. When we apply a potential difference between one of the electrodes and the mirror, electrostatic force attracts them toward one another and the mirror tilts.

In a typical mirror array, all of the mirrors are fabricated as a single electrical node. This node is grounded, and the electrodes are stimulated independently with analog DC voltages corresponding to the desired tilt angle. Since electrostatic force is always attractive, each mirror needs two drivers to tilt in both directions. Hinge stiffness and geometry determine the relationship between voltage and tilt angle.

One method of driving the micromirror, bipolar PWM (BPWM), uses square waves instead of proportional voltages to tilt the mirror. Instead of grounding the common node Vc, a 36kHz square wave toggles between zero and Vp-p, the high-voltage supply. The North electrode receives an identical square wave, but is phase-shifted with respect to Vc. The resultant potential difference between the common node and the North electrode, shown as (Vn * Vc), is a PWM signal whose amplitude is alternately Vp-p and *Vp-p with respect to system ground.

By varying the amount of phase shift, pulse width is varied and hence the rms voltage. Because the PWM frequency is 10 to 50 times higher than the mirror's mechanical-resonance frequency, the mirror acts as a mechanical low-pass filter and remains in a stable tilt position. The rms voltage across the mirror and electrode can vary between zero and Vp-p, but the average voltage is always zero.

Force will vary

In principle, the South electrode is driven with the complement of Vn--its pulse width--and hence its force will vary as the inverse of that on the North electrode. Besides simplifying the drive circuitry, this complementary scheme helps to linearize the tilt vs. phase-shift curve.

To realize complementary BPWM, Movaz has developed a chipset comprised of two all-digital ASICs: a low-voltage content-addressable memory array and a high-voltage level shifter. The CAM array receives up to 240 tilt coefficients from the system controller and stores them. Its outputs are the phase-shifted square waves. The high-voltage level shifter accepts the 5V square waves from the CAM chip and shifts them to amplitude Vp-p, producing a true and a complementary output for each input.

The ASICs are flip-chip-mounted directly onto the same silicon substrate that contains the MEMS electrodes, creating a compact multichip module. This MCM is wire-bonded to a PCB that fans out to a 35-pin connector for interface to the control electronics. Since signal demultiplexing takes place in the CAM ASIC, only 35 wire bonds are needed between the MCM and the PCB, even for large numbers of mirrors.

How gracefully do separate drive schemes scale as more MEMS mirrors are added to the array? For an array of one-axis mirrors, the BPWM approach adopted by Movaz was compared with spec-sheet data for a commercially available 32-channel high-volt amp and a 16-channel DAC chip. With one to eight mirrors, the number of driver chips required is equal, at two each. But after the ninth mirror is added, the DC system requires another D/A chip, then another D/A plus another high-voltage amp after the 17th mirror, and so on. In D-WDM products, you can add mirrors in blocks of 20, 40 or 96, corresponding to ITU grid channel spacings. At 40 mirrors, the DC drive requires eight chips and 81 wire bonds, vs. three chips and 35 wire bonds for BPWM. Thus, the BPWM driver scales better to large arrays.

As additional blocks of 40 mirrors are added, the differences become even more dramatic. Imagine an MCM containing 12 rows of 40 two-axis mirrors each in a BPWM implementation. To drive the 1,920 independent nodes on this array requires 16 chips and 36 wire bonds. The equivalent DC-voltage architecture required for this system would comprise 180 chips and 1,921 wire bonds. The wire bond count alone casts doubt on the viability of the DC approach.

Large chip counts also impact cost, board size and complexity. For the 480-mirror, two-axis example, the combined chip area would exceed 200cm2, excluding peripherals, and track count on the fanout PCB would be near 4,000. In systems requiring fine-angle control, EMI-induced disturbances in any of the myriad high-voltage or low-voltage analog signals may cause undesirable mirror tilts, further complicating the board designer's task.

Finally, the choice of drive scheme impacts power consumption and corresponding cooling requirements. Different mechanisms determine power dissipation in the DC and BPWM drives. Since the load is capacitive, the DC drive's thermal dissipation is dominated by internal bias currents, and scales linearly with chip count: each high-voltage amp adding 210mW and each D/A 110mW. For BPWM, power dissipation is primarily determined by CV2f dissipation in the high-volt circuitry. This allows the designer to trade power dissipation against two parameters: parasitic capacitance on the mirror array and PWM frequency. The latter parameter affects tilt precision, since precision of the phase shift relates to the ratio of the high-speed CAM array clock frequency to the PWM frequency. Calculated power dissipation for the two drive schemes rises as mirror count increases, for two levels off-PWM in the BPWM case. Assuming a capacitive load of 7.86pF per mirror, Vp-p of 200V and 12bit control resolution, the BPWM at both frequencies generates less heat than DC, reducing the cooling burden on the system.

- Michael Nagy

Movaz Networks Inc.





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