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Fujitsu extends AccelArray line

Posted: 02 Apr 2004 ?? ?Print Version ?Bookmark and Share

Keywords:fpga? asic? lsi logic? rapidchip? nec?

One of the selling points of structured ASIC architectures has been delivering far more performance than FPGAs: almost the same performance as cell-based ASIC designs in the same geometry. For most blocks in most applications, little is lost since structured ASICs are still more than adequate.

But there are exceptions. And not surprisingly, the industry is moving to address them.

The big exception all along has been LSI Logic's RapidChip family, which puts the bulk of its logic in diffused macroblocks so that for the intended range of applications all the critical paths will end up in diffused logic.

In recent months, structured ASIC vendors such as NEC and Fujitsu have moved circumspectly in the same direction, adding diffused functional blocks of increasing complexity. At the electronicaUSA with Embedded Systems Conference, Fujitsu announced a major step in this direction with two families of new structured ASIC devices: one incorporating a 200MHz ARM 9 CPU and the other including various combinations of Gigabit PHY blocks.

The ARM-armed device incorporates an ARM 926ES CPU core into a quite large structured ASIC to provide a very general solution to single-CPU SoC applications across a wide space. The 926ES is implemented with its MMU and 16KB of instruction and data caches, and the beginnings of an AMBA bus architecture are provided as well with an AHB switching matrix.

The chip differs significantly from the LSI approach in that it includes no diffused blocks that are really application-specific. Instead, Fujitsu relies on its extensive library of soft cores - more than 60 at last count - to fill out the rest of the CPU. This is true of CPU-specific blocks such as the actual bus implementation and AMBA peripherals. They are available as synthesizable IP rather than being part of the diffused core.

Significantly, Fujitsu is comfortable enough with the performance of its structured fabric to offer ARM and ARC processor cores, a DDR DRAM controller and MACs for bit rates up to 10Gbps in synthesizable form.

The canvas onto which this filling out will be done is substantial. Fujitsu rates the chip at 3 million ASIC gates and four megabits of on-chip memory. There are diffused, metal-configured I/O blocks that support PCI-66, PCI-X, HSTL/SSTL, and LVDS signaling.

The second addition of diffused functionality comes in a form that no one considers to be synthesizable: PHY blocks. Fujitsu has developed a three-mode Serdes and a pair of configurable PHY blocks.

The first of the PHYs, the S-PHY, is a 21-channel device that covers bit rates from 600Mbps to 800Mbps and standards including SPI4.2, SFI4, RapidIO and Hypertransport. The second, the four-channel G-PHY, covers the 622Mbps to 3125Mbps range and standards including XAUI, FibreChannel, RapidIO, PCI-Express, and CDR.

These blocks are available in various combinations on the five announced members of the new family. They range from the G30, with three of the 4-channel G-PHY blocks, 35,000 flip-flops and about 2Mb of memory to the G55, which boasts two G-PHY blocks, two of the 21-channel S-PHY blocks, 70,000 flip-flops and over 4Mb of memory.

All the devices are fabricated in Fujitsu's 110nm CMOS process. The structured ASIC fabric in each device offers the usual combination of features for the AccelArray family. The logic blocks are configured and interconnected in the final metal mask layers, and already have clock, power and DFT routing completed so that the user can focus on logic and systems design, not physical design.

Turnaround times can be as short as eight weeks, and Fujitsu said the maximum core system operating frequency is 333MHz.

- Ron Wilson

EE Times





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