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TI adds 6.25Gb serdes blocks to ASIC library

Posted: 13 Apr 2004 ?? ?Print Version ?Bookmark and Share

Keywords:texas instruments? ti? asic? serializer/deserializer interface?

Texas Instruments Inc.'s ASIC business unit has added 6.25Gbps serializer/deserializer (serdes) interfaces to its 90nm process library. At small feature sizes, designers can integrate up to 200 6.25Gb channels on one ASIC, with a typical power dissipation of 185mW per channel.

The serdes blocks use two-level binary signaling, and implement analog pre-emphasis on the transmit channel. On receive, a high-gain adaptive linear equalizer compensates for inter-symbol interference and crosstalk.

The process technology for the ASICs uses up to eight layers of metal, and integrates a low-k (2.8 k-value) organo-silicate glass dielectric. Core transistors are implemented in a plasma nitrided oxide. The serdes blocks are available for design starts immediately.

- Loring Wirbel

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