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TSMC readies new business strategy

Posted: 13 Apr 2004 ?? ?Print Version ?Bookmark and Share

Keywords:tsmc? 65nm test chip? semiconductor devices?

Taiwan Semiconductor Mfg Co. Ltd (TSMC) will unveil a revamped business strategy meant to take on the increasingly difficult task of designing, manufacturing and testing advanced semiconductor devices. At the same time, the company will announce that it has manufactured its first 65nm test chip.

TSMC's "platform" approach, which is announced at the company's technology symposium today (April 13, 2004), is meant to address the gap between chip design and manufacturing, which has worsened in recent years with the shift to 130- and 90nm process design rules.

The gap has been pegged as a root cause for fundamental changes that are reshaping the semiconductor industry, from a decline in the number of full-custom chips being designed to the scarcity of venture capital funding for startup chip companies.

At past symposia, TSMC has weaved in suggestions about how to address design-to-manufacturing problems within the framework of discussion about process technology. This year, design-for-manufacturing will be a central theme.

"What we have done is positioned our technology and design services into a holistic approach that we call platforms," said Chuck Byers, director of brand management at TSMC. "Success is going to depend on something more than process technologies. What is required is an integrated environment for the backend, assembly, test, packaging and libraries. All that needs to be addressed up front."

The company said it has tweaked its marketing focus accordingly, appointing two senior managers to lead the platform effort. Ken Chen, who was overseeing business development for TSMC in Japan, is now director of mainstream technology platform marketing. John Wei, the former director of Fab 5 in Hsinchu, Taiwan, has been reassigned to director of advanced platform marketing.

As part of the plan, TSMC will present a new set of design guidelines for its most advanced process technologies, particularly for 0.13?m and below. Some of the structured design rules "are absolutely required to achieve certain yields; others are suggested for certain yields," Byers said.

The platform design strategy is being rolled out as the company prepares to disclose plans to fabricate chips based on 0.065?m design rules. The company's most advanced chips today are based on 90nm design rules, which are slated to move into full production by the second half of this year. At the symposium, the company is expected to discuss technical details for its "half node" 0.11?m process technology and new ways to support older nodes starting at 0.18?m and greater, Byers said.

- Anthony Cataldo

EE Times





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