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Startup takes a novel design-for-yield approach

Posted: 14 Apr 2004 ?? ?Print Version ?Bookmark and Share

Keywords:anchor semiconductor? nanoscope? silicon design-rule-checking tool? silicon drc tool?

With a mission of improving semiconductor yields for nanometer-scale ICs, startup Anchor Semiconductor Inc. has quietly begun shipments of NanoScope, a tool that provides full-chip, post-resolution-enhancement technology verification. NanoScope is the market's first silicon design-rule-checking (DRC) tool, Anchor said.

Launched in 2000 by entrepreneur David Tsang and Chenmin Hu, privately held and privately funded Anchor Semiconductor employs more than 20 people, about half of them R&D engineers in Shanghai, China. Anchor's key algorithms and software modules have been developed at its headquarters in Sunnyvale, Calif., but the Chinese team "will make more contributions in the future," said Hu, Anchor's chief executive officer, who previously co-founded analog modeling company Symmetry Design Systems Inc. and founded IC layout company Stanza Systems Inc.

"We really target mission-critical problems that affect yield, so primarily we're targeting the patterning process," said Cliff Ma, vice president of marketing at Anchor. Designs below 130nm can experience substantial yield losses when transferring a layout pattern onto the wafer, he said.

With "subwavelength" lithography, a pattern drawn on a layout design can be very different from what gets printed on a wafer. That's why most semiconductor manufacturers use resolution-enhancement technologies such as optical proximity correction (OPC) and phase-shift masks at 130nm and finer processes.

Existing RET tools are good enough for designs down to 130nm, but not below, Ma said. "The window becomes so small, and layout patterns become so complicated, that the process cannot tolerate any marginal OPC errors, either under- or overcorrections," he said. NanoScope complements RET tools by verifying their output, he said.

NanoScope has two functions, Ma said. One is independent, full-chip, post-RET verification, used before making masks. Another is identification of "hot spots" in a pre-OPC design, such as "OPC-unfriendly" structures that make it hard to add RET to a layout.

While providers of RET tools also offer DRC, that's not sufficient, Ma said, because when RET and DRC tools come from the same vendor, "they're really checking against themselves." Moreover, NanoScope offers an "intelligent" approach based on simulation rather than a rules-based approach, he said.

NanoScope takes in GDSII files and builds a process model. It then inspects the chip, using two kinds of models: the after-develop-image models used by most commercial tools, and after-etching-image models that, according to Ma, are also crucial but seldom used.

NanoScope searches for defects such as bridging, breaking, via contact and closure, and gate-related problems. Its inspection is flat, but its analysis and reporting are hierarchical, Ma said. When it outputs a design's defect locations and their severity, users can graphically navigate through different levels and layers of the chip. NanoScope reports but does not correct the errors.

Today, Ma said, NanoScope is aimed at semiconductor foundries and device manufacturers. Anchor is working on a yield-enhancement product aimed more specifically at design engineers, he said.

"We believe that each fab is going to run this tool like they run DRC," he said. "If you count the number of DRCs in a fab, you can get to the same number of silicon DRCs."

A new chapter in Mark Rencher's on-line book at EEdesign, "What's yield got to do with IC design," details the use of NanoScope at Xilinx. Co-authored with Chenmin Hu, the chapter begins at page 43.

- Richard Goering

EE Times

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