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Cortina obtains $20M Series B funding

Posted: 15 Apr 2004 ?? ?Print Version ?Bookmark and Share

Keywords:cortina systems? taiwan semiconductor? risc processor? silicon?

Cortina Systems Inc., a startup that demonstrated remote packet ring silicon last year, has gained $20 million in Series B financing to be use to extend its mixed-signal design expertise into integrated devices for the transport and enterprise-aggregation markets.

The company also announced a number of executive appointments.

Amir Nayyerhabibi, chief executive and founder of Cortina, said all initial investors participated in Series B, including round leader Kodiak Venture Partners as well as Morgenthaler Ventures, Redpoint Ventures, El Dorado Ventures, and Invesco Private Capital.

Joining this round was Hotung Capital Management Inc., a venture capital arm of Taiwan-based Hotung International Co. Ltd.

"The Taiwan ties are significant in many ways," Nayyerhabibi said, referring to Cortina's early fab alliance with Taiwan Semiconductor Mfg Co. Ltd, which produced the resilient packet ring (RPR) device that Cortina demonstrated last June.

Investor Hotung a partner with Cortina on several fronts, and will help the company into the Chinese semiconductor market, where interest in metropolitan multiservice access is booming, Nayyerhabibi said.

Cortina has meanwhile appointed Bruce Margetson, former chief financial officer at Luminous Networks Inc., as its CFO. Behrooz Yadegar, former senior VP of engineering and operations at MediaQ Inc., has joined Cortina as VP of operations.

Though Nayyerhabibi and Yadegar worked together on designs of the MIPS R3000 and R4000 processors at MIPS Technologies Inc. and Silicon Graphics Inc., Nayyerhabibi said Cortina will not dive into control-plane RISC processor integration. "We will assist a Layer 3 network processor function where appropriate, but we want to keep a very clear vision of where Layer 3 functions belong," Nayyerhabibi said. "Our main goal is to integrate a variety of Layer 2 devices, including Ethernet and RPR, with world-class physical-layer functions for high integration and low-power dissipation at the line-card level."

The company will spend the rest of 2004 integrating new physical-layer blocks, including advanced serdes cores and interfaces supporting the XFP serial standard, with Layer 2 cores specific to certain markets.

- Loring Wirbel

EE Times





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