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TSMC, Cadence disclose reference flow integration plan

Posted: 19 Apr 2004 ?? ?Print Version ?Bookmark and Share

Keywords:tsmc? cadence design system? rtl compiler? reference flow?

Taiwan Semiconductor Mfg Co. Ltd (TSMC) and Cadence Design Systems Inc. have announced their planned integration of Cadence Encounter RTL Compiler into TSMC's next-generation reference flow.

According to the companies, the inclusion of RTL Compiler addresses key nanometer performance goals, improves timing closure, reduces device area and lowers power consumption for complex multi-million-gate SoCs. RTL Compiler effectively uses TSMC's multiple-Vt (voltage threshold) libraries to optimize performance and leakage power in a single-pass optimization flow.

"We intend to instill designer confidence that high quality silicon is achievable, despite escalating chip complexity," said Genda Hu, VP of corporate marketing at TSMC. "Integrating Cadence's RTL Compiler into our next-generation Reference Flow should help resolve challenging design issues and leverage TSMC libraries," Hu added.

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