Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
EE Times-Asia > Embedded

Startup's tool adds hardware validation

Posted: 21 Apr 2004 ?? ?Print Version ?Bookmark and Share

Keywords:carbon design systems? designplayer? presilicon software validation? emulator?

EDA startup Carbon Design Systems Inc. has expanded the capabilities of its DesignPlayer models to perform hardware validation as well as presilicon software validation. DesignPlayer works at speeds comparable to hardware-based emulators but costs less, the company said.

The initial release of DesignPlayer was designed to give software engineers a jump on validating software drivers, diagnostics, and firmware. At launch last fall, the product was said to be 50 to 200 times faster than event-based simulators. Now the expanded models can be used for hardware validation as well, said Steve Butler, president and CEO of Carbon. A DesignPlayer model, which is an API-type wrapper, tests a chip design in the context of an entire system, he said.

"A typical company today has at least three [design] models," said Butler, a former executive at emulation vendor Quickturn Design Systems. "They have a simulation model for block and chip level; some kind of prototyping such as a C model, breadboard or emulator; and they almost always go to silicon for software and custom validation. That's three different models with varying debug capabilities and varying accuracy. Now that can be dealt with using one presilicon engine. The tool runs at multiple kilohertz, is cycle- and register-accurate and is a software-only solution."

DesignPlayer creates a run-time linkable object or model of a chip or core that can be compiled directly from register transfer level with Carbon Design's SpeedCompiler tool. DesignPlayer can be plugged into hardware regression environments and driven by a variety of testbenches. It provides a 10x or greater performance gain over current solutions, Butler claimed.

Alan Swahn, VP of marketing at Carbon, said DesignPlayer is used after designers have developed the RTL for a complete chip or IP block. Users feed the RTL version of the design into SpeedCompiler and the tool creates a DesignPlayer model that can be used with popular verification environments. DesignPlayer works with transaction-level, behavioral Verilog, C, C++, and SystemC languages.

Later this year, Carbon plans to add support for behavioral VHDL.

Verification teams that use DesignPlayer with C, C++ or transaction-level testbenches and without an event-based simulator can achieve a tenfold to twentyfold regression performance boost over RTL simulation while maintaining cycle and register accuracy, Swahn said.

For example, the tool will help designers overcome a nagging obstacle when creating a model of an ASIC or system- on-chip in SystemC and then an RTL implementation of the model, Swahn said. Designers are handcuffed if they try to simulate the RTL models with SystemC, he said, because the event simulator running the register-transfer version slows the SystemC model linked to RT simulation.

With DesignPlayer, users create an RTL model and compile it into a model. It runs at comparable speeds to the SystemC version, delivering a performance increase without losing accuracy, Carbon said.

Prices for Carbon's SpeedCompiler start at $150,000. DesignPlayer engines used for development are priced under $10,000 per seat for high-volume purchases, while IP distribution versions approach $1,000 per seat.

- Mike Santarini

EE Times

Article Comments - Startup's tool adds hardware validat...
*? You can enter [0] more charecters.
*Verify code:


Visit Asia Webinars to learn about the latest in technology and get practical design tips.

Back to Top