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WED module targets memory system apps

Posted: 20 Apr 2004 ?? ?Print Version ?Bookmark and Share

Keywords:white electronic designs? ddr sdram? memory module? w3eg72255s-d3?

The 2GB DDR SDRAM registered ECC memory module from White Electronic Designs Corp. is claimed by the company to provide maximum performance for memory system applications.

JEDEC compliant, the module is a 2 x 256M x 72 Double Data Rate (DDR) SDRAM memory module based on 512Mb DDR SDRAM components. It consists of eighteen 256M x 4 stacks in 66-pin TSOP packages mounted on a 184-pin FR4 substrate, and is structured as two ranks of 128M x 72 DDR SDRAM.

Design offers precise cycle control

With a designated part number of W3EG72255S-D3, the product features DDR architecture: DDR200, DDR266, and DDR333 JEDEC design specifications. It offers bidirectional data strobes (DQS), differential clock inputs (CK and CK#), programmable Read Latency 2, 2.5 (clock) and Programmable Burst Length (2, 4 and 8). Additionally, the device features include auto and self refresh, serial presence detect, edge aligned data output and center aligned data input.

According to WED, the synchronous design allows precise cycle control with the use of a system clock. Data I/O transactions are possible on both edges and Burst Lengths allow the same device to be useful for a variety of high bandwidth, high performance memory system applications.

Measuring 30.48-by-133.48mm, the module has a maximum 6.35mm package body thickness, and is priced at $669 each.





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