Sun shuffles Sparc lineup: Drops two, adds two

Under budget and manpower pressures, Sun Microsystems Inc. has redrawn the road map for its Sparc microprocessor, killing two high-profile CPUs slated for 2005 and adding two others. The moves point in part to a broader trend at Sun and its competitors to embrace multithreaded, multicore architectures in place of traditional CPU design techniques.

Sun canceled its UltraSparc V, a dual-threaded CPU that was going to be the first Sparc with an out-of-order execution pipeline. The company will emphasize Rock, a recently disclosed chip that will pack a combination of about 10 cores and threads on a 65nm die. Shipments in systems are expected in 2007.

Filling the gap, Sun will roll out UltraSparc IV+ next year, a 90nm version of its dual-core UltraSparc III chip with an on-board level-two cache.

Separately, Sun canceled Gemini, a low-power, dual-threaded CPU aimed at server blade systems for 2005, relying instead on greater use of UltraSparc IIIi+ and X86 processors in server blades.

The company remains committed to Niagara, a 90nm multiprocessor-on-chip that packs eight cores running four threads each. The part is aimed at server blade systems that will ship in 2006.

"These are not decisions we make easily," said Marc Tremblay, chief architect of Sun's processor group. "They involve years of R&D and lots of people who are affected. A significant portion of these people are being deployed on Rock and Niagara families," Tremblay added.

Sun announced plans to lay off 3,300 workers on April 2 but has not yet disclosed details about the layoff.

Sidestepping a bottleneck

Analysts and competitors said Sun's new road map makes sense. Even though the UltraSparc V design had been sent to its fab, Texas Instruments, Sun would have faced a long verification cycle for the new and complex pipeline, said Nathan Brookwood, principal of market matcher Insight64.

The out-of-order pipeline does not benefit server workloads targeted by Sun as much as it does desktop applications. Nevertheless, Intel Corp.'s Pentium and IBM Corp.'s Power architectures both sport out-of-order execution pipelines.

Rock will use multithreading to bolster single- and multithread performance of the CPU in a way that achieves some benefits of out-of-order execution but uses less die area. Tremblay said he will disclose details of Rock in a June 23 keynote at the International Symposium on Computer Architecture in Munich.

Intel recently demonstrated a technique it calls asymmetric multithreading on a prototype Itanium processor that uses as many as 24 short "helper threads" generated by a compiler to pre-fetch and speculatively execute data, improving a CPU's single-thread performance. The technique will appear in Xeon and Itanium CPUs "very soon," said Justin Rattner, director of Intel's microprocessor research lab.