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'Algorithm-to-tapeout' synthesis rolls

Posted: 03 May 2004 ?? ?Print Version ?Bookmark and Share

Keywords:ppa? synfora? ip? block? c?

Claiming to offer the first "algorithm-to-tapeout" synthesis tool, startup Synfora Inc. unveiled a tool that lets users design compute-intensive blocks from C-language algorithms. Pico Express works with a customizable intellectual-property (IP) block called a Pipeline of Processor Array, or PPA.

Synfora's technology is based on the Program-In, Chip-Out (Pico) project from Hewlett-Packard Co.'s research labs. Though the Pico project was discontinued after HP's merger with Compaq Computer, Synfora obtained related IP and patent rights from HP, which holds a minority stake in the startup.

Key to Synfora's approach is its combination of tools and IP. The PPA supports the design of compute-intensive blocks such as MPEG decoders and Viterbi decoders. Synfora also is developing a very long instruction word (VLIW) processor block that can handle control-intensive applications, but that will probably take another year, said Simon Napper, president and CEO of Synfora.

"Even if we had it today, the VLIW would be too big a step for people to start with," Napper said. "Designers are used to RTL, and we need a step-by-step process so they can learn to write C for hardware and see what the benefits are."

One benefit Pico Express offers, Napper said, is design space exploration. He noted that the tool can produce more than 200 implementations of a given algorithm, and users can pick the best choice in terms of performance and area. It takes just a few minutes to generate each possible implementation, he said, along with Verilog RTL code, synthesis scripts and a testbench.

Pico Express takes in algorithmic C code. It needs to be expressed as a sequence of nested "for" loops, which is typically how compute-intensive blocks are programmed, Napper said. There are some restrictions. For example, the code can't contain pointers or procedure calls.

Designers also specify the performance and memory bandwidth requirements. Napper said the tool currently assumes the use of the 0.13m process of TSMC. With a different foundry, he said, the results could be slightly different. If a customer has a captive fab, Synfora can re-characterize the IP to that facility's process.

The compiler does loop transformations and instruction-level transformations to gain the maximum advantage of parallelism. It then looks at performance and resource requirements. It allocates resources and performs scheduling and then generates Verilog RTL.

Pico Express also generates a Verilog testbench from the input code provided to test the C-language algorithm. It adds what Napper called "perturbation testing" for pipelines and FIFOs, which are not explicitly represented in C.

With about half the blocks that Pico Express has tackled, it has shown a 40 percent to 50 percent improvement in area compared with RTL coding, Napper said. With the other half, it's within about 2 percent of RTL coding.

Pico Express is already available and priced at $125,000 for a design project license.

- Richard Goering

EE Times





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