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Xilinx rolls out CPCS reference design

Posted: 04 May 2004 ?? ?Print Version ?Bookmark and Share

Keywords:xilinx? configurable physical coding sublayer? cpcs? reference design? pcs block?

Xilinx Inc. has announced the immediate availability of a free fully functional Configurable Physical Coding Sublayer (CPCS) reference design for a multi-mode PCS block implemented in Xilinx Virtex-II Pro FPGAs.

The CPCS can be dynamically configured to support three types of PCS layers including Fiber Channel (1.0625Gbps and 2.125Gbps), Gigabit Ethernet (1000BASE-X), and ESCON/SBCON (200 Mbps). The reference design is suitable for applications including Ethernet/Fiber Channel switches, multiservice provisioning platforms (MSPP), SONET/SDH terminals, Add-Drop Multiplexers (ADM), cross connects, CWDM/DWDM transport equipment, and IP routers.

Dynamic protocol selection is fully integrated into the control plane running on the Virtex-II Pro embedded PowerPC 405 processor. The tight coupling of the configurable embedded RocketIO MGTs provides the required serial data rates ranging from 200Mbps to 2.125Gbps. According to Xilinx, this would not be feasible with an external serdes solution.

The fully documented CPCS reference design is available free of charge from the company's website.





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