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SiRES chip integrates VCSEL driver, LVDS interface

Posted: 06 May 2004 ?? ?Print Version ?Bookmark and Share

Keywords:sires labs? optical transmitter? receiver? srl3101ns?

Targeted at very short reach (VSR) applications, the new single-chip integrated optical transmitter (Tx) and receiver (Rx) from SiRES Labs functions at 3.125Gbps per channel.

The optical transceiver chip integrates the transimpedance amplifier (TIA), limiting amplifier (LA), VCSEL driver, and LVDS interface typically available as individual components. Designed for speeds ranging from 1Gbps to 3.125Gbps and consuming 250mW of power under maximum operating conditions for both transmitter and receiver functions, the SRL3101NS features both digital and analog control and monitoring functions, and is targeted for use with VCSELs and PIN/APDs in VSR applications such as Gigabit Ethernet, SONET VSR links, intra-system, backplanes, SAN, Fibre Channel, and terabit routers and switches.

With a single 3.3V operation, the chip features a peak-to-peak jitter of 20ps (PRBS23), modulation and bias currents of up to 10mA (with each controllable via an external analog voltage or digitally through the internal registers via a standard I?C interface), an integrated temperature sensor, and an internal closed-loop feedback for temperature compensation without the need for an external monitor photodiode.

Other features include an adjustable VCSEL diode monitor comparator window, tolerance of photodiode input capacitances of up to 1pF, input current range from 15mA to 400mA, a two-step threshold-selectable low-input signal detect feature, and an average input current monitor output. The digital status signals are accessible via internal registers or through the serial digital interface.

Offered in a die measuring 1.6-by-2.2mm, the SRL3101NS is available packaged or as bare die with large bond pad pitches. Using the CMOS process, the chip has been designed using the company's dynamic self adaptive biasing (dSAB) technology that compensates for process- and temperature-induced parametric variations and allows for a higher yield of analog circuits in CMOS.

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