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Rambus offers interface IP for DDR, DDR2 DRAMs

Posted: 12 May 2004 ?? ?Print Version ?Bookmark and Share

Keywords:rambus? ddr? ddr2? dram? gddr?

Breaking with a tradition of proprietary interfaces, Rambus Inc. for the first time is offering interface intellectual property (IP) for industry-standard double-data-rate, DDR2 and XDR DRAMs. The family of interfaces, some members of which are available now, will be provided as hard IP with some configurable features, initially for the 130- and 90nm processes of Taiwan Semiconductor Mfg Co. Ltd.

"We see SoC designers growing increasingly nervous about the accelerating frequency of DRAM interfaces," said Rich Warmke, director of marketing for Rambus. "In many cases teams who will be using fast DDR2 devices or who are looking at the XDR [expanded-data-rate] proposal may find that the DRAM interface contains the fastest signals entering or leaving their chip."

Warmke said that some design teams have experience with designs in the gigahertz range, and are comfortable acquiring controller and interface IP, integrating delay-locked loops (DLLs) into it and verifying the resulting complex interface.

But other teams are only just moving up to these kinds of frequencies. "We see a number of system designers who are contemplating moving up to GDDR for cost reasons," Warmke said, referring to graphics-DDR devices. "They may not need the increased performance over vanilla SDRAM, but they see the handwriting on the wall as the sweet spot in the memory market shifts toward DDR."

Rambus can help both kinds of teams, Warmke said. "We can offer hard-IP interfaces that don't require the design team to get under the hood and modify DLLs or chase down critical timing paths. And we can bring to their design our own very considerable expertise for the problems on both sides of the interface: experience in the system-level questions necessary to make the interface and controller meet the system's memory access requirements; and experience in the package and pc-board design and analysis necessary to get the signals safely between the chip and the memory devices."

Rambus intends to offer two families of interface cells: one for consumer devices and graphics accelerators; and the other for interfaces to bulk memory in PCs, servers and the like. In consumer and graphics applications DRAMs are soldered down in close proximity to an SoC, providing a fixed, carefully controlled electrical path between interface IP and memory ICs. In bulk-memory applications, the path runs through connectors and DIMMs, with considerably more parasitics and variability.

Rambus designers felt that the two environments could not be bridged using a single-interface cell design without unacceptable compromises. So the company created an output structure for each.

Within each family will be two branches: a mainstream profile and a performance profile, each a different hard macro. In the consumer/graphics family, the mainstream interface will support GDDR1 at 400MHz to 1GHz and DDR2 at 400MHz to 800MHz. The cell is available for TSMC's 130nm process. In the third quarter Rambus expects to release the performance version, supporting GDDR1/3 at up to 1.6GHz and DDR2 at 400MHz to 800MHz.

As an added differentiation, the performance cell will also support Rambus' recently announced XDR DRAM interface. This is no mean feat, Warmke said, as GDDR is a single-ended signaling scheme while XDR is a 4GHz (with plans for 8GHz) differential-mode interface. Supporting both with a single cell, and allowing a user to select the mode at startup, meant remapping the interface pins so that single-ended I/Os and reference voltage inputs became signal pairs.

This also required close attention to the allocation and routing of signals within the interface itself, as the differential signals need to be paired up in routing, but the single-ended signals need to be separated from their neighbors as much as possible. Rambus designers accomplished the task, however, creating an interface cell that is register-configurable for either spec.

Thus system designers can use a single set of pins on one version of their SoC for boards stuffed with either GDDR or XDR memories. This allows a vendor to offer a huge range of memory bandwidth with a single-chip design and only limited changes in board art.

Bulk-memory versions of these cells will follow. This presents a complex product-management problem, since Rambus could potentially find itself with four different cells to support in several foundries. Warmke said the strategy will be to start with foundries and processes that are likely to serve a range of design teams. Then additional foundries and even captive processes could be supported by special arrangement-that is, for extra bucks.

Rambus' silicon validation methodology is rigorous, requiring numbers of split-lot test chip runs and extensive characterization. This conservatism will have to relax a little to support such a diverse product line.

- Ron Wilson

EE Times

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