Framer/mapper cuts evolutionary path for Sonet design

Galazar Networks Inc. has added a framer/mapper device called the VersaNode to its Sonet/SDH chip family that integrates pointer-processor capabilities and an SPI-3 interface, thus providing higher integration and an evolutionary path to metro-equipment designers.

Like other telecom chip suppliers, Galazar has been peddling virtual-concatenation (Vcat) framer/mapper devices to Sonet equipment vendors over the past few years to support the delivery of Ethernet services over existing Sonet links. But now that Sonet/SDH networks are becoming more packet-enabled-through either Vcat or dedicated Ethernet links-carriers are looking for solutions that support Ethernet today and a path for additional services tomorrow.

"Carriers need to support the evolution of their networks," said Matthew Coakeley, director of applications engineering at Galazar. "Now we need to show that we understand what problems are coming in the future."

Two problems related to the management of virtual-concatenation traffic are emerging. First, the addition of Vcat can lead to more traffic that must be terminated at an aggregation box, causing potential processing headaches. At the same time, Vcat may require carriers to perform Layer 2 or 3 processing on Vcat streams.

By adding the SPI-3 interface to the VersaNode product, Galazar is helping designers combat both of these challenges. Through the SPI-3 interface, designers can add an external network processor that can be used to bundle multiple Vcat streams onto a single Vcat group, thus reducing network load.

The net processor can also be tapped to provide traffic management capabilities to a system, thereby allowing designers to assign classes of service on a per-Vcat-stream basis, Coakeley said.

Galazar said that it is also addressing the future needs of carriers by upping the integration levels in the VersaNode device. Metro-box developers typically need a three-piece chipset, consisting of a framer, a mapper and a pointer processor, to add packet capabilities to a Sonet/SDH line card. With VersaNode, Galazar has put the framer and mapper in one device and combined them with a pointer processor that can process high-order and low-order streams.

Single brain "Using this chip, designers can build a full add-drop multiplexer with a single-chip brain," Coakeley said.

VersaNode also includes two Gb Ethernet ports, six Fast Ethernet ports, 28 DS1/E1 ports and eight DS3/E3 ports. The chip provides a generic 16-bit microprocessor interface and a telecom bus that can be clocked up to 622Mbps; the telecom bus in the company's previous framer/mapper devices capped out at 155Mbps.

For packet encapsulation, the chip supports the generic framing procedure, the link access procedure for SDH and RFC1662 PPP. It also provides optional support for the link capacity adjustment scheme, which allows carriers to adjust the size of Vcat groups dynamically.

The VersaNode device was developed in a 0.13?m process at Taiwan Semiconductor Manufacturing Co. Ltd; it is expected to draw between 3W and 4W. The chip is being delivered to alpha customers now and will be generally available in the first quarter of 2005.

- Robert Keenan

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