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Tharas spins new accelerator box

Posted: 13 May 2004 ?? ?Print Version ?Bookmark and Share

Keywords:tharas systems? hammer? hardware accelerator? verilog? vhdl?

Tharas Systems Inc. has released a new version of Hammer, its event-driven hardware accelerator, that it says can compile Verilog, VHDL or mixed-language designs at rates of 20 million to 50 million register-transfer-level equivalent gates per hour on a single workstation, offering incremental design and testbench compilation performance.

"With this version of Hammer we have worked very hard to improve design turnaround time, i.e., how fast can you bring a 20- to 30-million-gate design into Hammer, do a full compile, isolate a bug, fix it and turn it around incrementally," said Sanjay Sawant, director of marketing and business development at Tharas. The result, he said, is "true incremental compiles for the design as well as the testbench."

Sawant said the new version of Hammer will not require users to recompile an entire design if they can locate a small 5,000- to 10,000-gate problem. They can merely isolate the problem areas, recompile those parts of the design and then link them to the rest of the design, he said.

"We can also just recompile part of your testbench and link it to the rest of the testbench," Sawant said. "It tremendously improves productivity."

The Hammer line of hardware accelerators relies primarily on custom processors rather than FPGAs to read designs and accelerate commercial simulators from Cadence, Mentor, and Synopsys. The use of these custom processors for most design storage and processing functions delivers capacity and speed, Sawant said.

While custom processors do most of the work, the Hammer 100 system also includes a Runtime Control Unit module that contains four Virtex-II Pro FPGAs from Xilinx Inc. and 4GB of memory, Sawant said. The memory can be used to implement verification stimulus, while the system uses an embedded PowerPC in the Virtex-II Pro devices to speed the arithmetic functions commonly needed to verify graphics chips and DSPs, he said.

Hammer 100 now includes debug capabilities to handle concurrent, parallel and progressive waveform conversion to such industry-standard formats as fast-signal database, value change dump or VCD post-processing data.

Hammer 100's concurrent-waveform conversion capability compresses trace data and concurrently converts that data into waveforms. Sawant said this feature allows designers to start debugging with a portion of the waveforms while more waveforms are generated as accelerated verification proceeds. Similarly, the system's parallel-waveform capability allows the user to make parallel conversions of compressed simulation trace data dumps across a network of workstations.

Sawant said the progressive-waveform converter can be used during active debug sessions, allowing a verification engineer to save relevant trace data only when simulation fails or does not meet expected results. Users may choose to save signals for a certain number of clock cycles or to save trace data sets for the times when simulation fails, he said.

Hammer 100 also supports Verilog 2001, the precursor to the SystemVerilog language. Hammer 100 operates under Linux and under 32-bit and 64-bit versions of Solaris.

The entry-level Hammer 100 starts at $144,000 for a 2 million-gate system. Customers can obtain versions of Hammer 100 with a capacity of 30 million gates at an extra cost. A 32 million ASIC gate time-based subscription is $588,000 per year. Users can also link several Hammer 100s to make a 128-million-ASIC-gate system, the company said.

- Mike Santarini

EE Times





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