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Silicon modeling in the nanometer era

Posted: 14 May 2004 ?? ?Print Version ?Bookmark and Share

Keywords:silicon? nanometer? interconnect? route? layer?

Rey: Designs are failing first silicon at an alarming rate.

As recent experience at 130nm revealed, signal integrity and timing closure are significant issues in nanometer technology. With 90nm in production and 65nm on the horizon, designs face increasing challenges that impact their success: finer line widths, longer interconnect, more routing layers and more analog content.

Though more functionality can be packed onto a single chip, designs are failing first silicon at an alarming rate. Studies show more than half fail because of functional flaws. Designers are not getting an accurate answer to the question, "How will my design work and will it yield?"

What are the issues? Primarily, critical first-order physical effects and design complexity. Dishing the metal layers changes a line's resistance and capacitance depending on local metal density. Contacts and vias, once ignored, add to total interconnect capacitance. The coupling capacitance percentage rises as a percentage of overall capacitance. Line-width variations and optical and process effects, applied post-layout, are also factors.

Moore's Law market pressure is not entirely to blame. Inadequate methods to deal with these new complexities have also contributed.

For years, EDA tool makers focused on front-end tools that could help create large, complex designs. Unfortunately, the infrastructure for back-end parasitic extraction and analysis tools fell behind, denying designers accurate and comprehensive silicon-modeling data. Even at 0.35?m and 0.25?m, when designs could be manufactured as drawn, parasitic effects were an issue. But they become more pronounced as process technology shrinks.

Traditional extraction tools focus on gates, ignoring the growing portion of chip area going to memory and analog blocks. Traditional tools also are specialized. For instance, analog designers require accuracy to the transistor level.

Since each analog block has unique characteristics, the extraction tool must investigate all circuit data, including nets in a small cell, select nets on a block and clock nets on larger designs. Digital designers will trade some accuracy for speed and performance, using a gate-level extraction tool that assumes cell characteristics.

Specialized extraction tools force custom analysis flows. Each analysis - power, noise, static and dynamic timing, signal integrity requires separate extraction runs, creating the "design pain" of managing multiple runs and rule decks. Advanced manufacturing adds hardships for extraction tools. Conformal dielectric layers, copper wiring and non-rectangular cross sections must be modeled correctly to see the interconnect effects.

Without tools or flows to properly do silicon modeling in nanometer designs - that is, the ability to characterize device performance as implemented in silicon - chips have been prone to failure and costly respins. With $1 million mask costs, profit is at risk.

What can be done? For effective nanometer silicon modeling, tools must measure and extract what has not been measured and extracted before. That will generate statistics to analyze the barometers controlling performance and yield. Fortunately, back-end tools are at a point where they can provide a deeper understanding of process variations; a way to measure, verify and modify; and are able to predict more accurately the performance of a device as implemented in silicon.

Such tools offer four main capabilities: robust device extraction to measure (not assume) device parameters; parasitic extraction for both gate- and transistor-level data; tight integration between the tools and the layout environment to allow back annotation to the source schematic; and integration to mixed-signal analysis tools. Without those abilities, nanometer silicon modeling is just another buzzword. With those capabilities, designers will more likely get an answer to the query, "Can I manufacture with confidence?"

- Juan Rey

Director of Engineering

Mentor Graphics Corp.

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