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EDA vendor, Accellera moves place SystemVerilog at crossroads

Posted: 19 May 2004 ?? ?Print Version ?Bookmark and Share

Keywords:systemverilog? eda? accellera? ieee 1364?

Two new developments raise questions about whether the emerging SystemVerilog language is heading for greater harmony or further acrimony.

An ad hoc group of EDA vendors Friday, May 14, 2004, called for a phased implementation of portions of SystemVerilog. Separately, EE Times has learned, the Accellera standards organization may be reconsidering its donation of SystemVerilog 3.1a to the IEEE 1364 working group and looking to form a separate IEEE committee.

Five EDA companies announced a proposal for a "SystemVerilog implementation working group" that will promote a phased, coordinated implementation of SystemVerilog design and assertion constructs. The intent is to avoid the kind of chaos that followed Verilog 2001 standardization, which still suffers from spotty and inconsistent implementation among EDA vendors.

The group, however, includes two EDA companies who were formerly openly skeptical about SystemVerilog - Cadence Design Systems and Verisity - and does not include Synopsys Inc., which is well ahead of most other vendors in SystemVerilog implementation.

Dennis Brophy, chair of the Accellera standards organization, questioned the need for the new group and noted that it doesn't call for implementation of the language's testbench constructs.

Meanwhile, Accellera is reportedly debating whether to turn SystemVerilog 3.1a over to the IEEE 1364 working group, the standards body directly responsible for Verilog. Some members of Accellera apparently want to find a way to bypass that group, which has been at odds with Accellera in the past. But some observers fear any such action could lead to incompatible versions of Verilog.

The vendors behind the proposed SystemVerilog implementation working group are Cadence, Verisity, Magma Design Automation, 0-In Design Automation and Novas Software. Consultant Stuart Sutherland is acting as a spokesman, and has agreed to serve as chairman of the proposed working group. Simon Davidmann, developer of the Superlog language, has agreed to chair a user technical advisory committee.

"My perspective, as a user, is that if there's a new feature in the language, I can't use it until it has fairly widespread support from software tools," said Sutherland. "Even now it's difficult to use a lot of Verilog 2001 features because there isn't full support across all the different tools. It hurts all EDA vendors to not have a synchronized approach to adding new features to a language."

Sutherland offered a preliminary proposal for a phased, coordinated implementation of SystemVerilog. It starts with convenience and productivity extensions for modeling, then moves on to RTL modeling and synthesis, data encapsulation, assertions and abstract modeling. No timetable has been set for these various phases.

The ad hoc group is also calling for the development of a common, interoperable test suite to verify compliance with SystemVerilog features. "This will help build user confidence, since an EDA vendor can prove they support a feature," Sutherland said.

The intent of the group is to become part of the standards process, and Sutherland said he "fully expects" that it will become an Accellera committee. Brophy didn't close the door to that possibility, but he appeared far from convinced there's a need for the new group.

Brophy said the group appears to be saying that vendor and user support for SystemVerilog hasn't happened yet. In reality, he asserted, it happened about two years ago. He further noted that the group is only calling for implementation of a subset of SystemVerilog, and that its phased roadmap may be well behind what's actually happening in the marketplace.

"Slow moving is the last thing you want in the world of EDA, and when I read this statement, there's a slow moving aspect of it in that they've ignored the whole testbench area of 3.1a," Brophy said. "The market may seem messy, but it's actually better at dealing with revolution than standards organizations and ad hoc groups like this."

It is notable that neither Mentor Graphics nor Synopsys, who are far along with their own SystemVerilog 3.1a implementations, are part of the new group.

"Detailed roadmaps are already published by more than 30 vendors on the web site reflecting what customers are requesting, and that is support for the entire SystemVerilog 3.1 standard, not a subset," said Rich Goldman, VP of strategic market development at Synopsys.

"Our viewpoint is that SystemVerilog needs to come out in one piece," said Robert Hum, VP and general manager of Mentor Graphics' design verification and test group. "I'm worried that an initiative like this wants to slow things down that don't need slowing down."

But the initiative is not an attempt to slow anything down, Sutherland insisted. "It will speed up user confidence and adoption. It's good for Synopsys and every other company," he said.

Davidmann said the user technical advisory committee will seek a "consensus" of what features the users want, and in what order. "Everyone wants structures and interfaces, and they want them quickly," he said. "What people want is coherence in a development plan."

SystemVerilog conversion?

Part of the irony behind the proposed working group is that the two vendors who appear to be taking the strongest role, Verisity and Cadence, were the strongest SystemVerilog critics in the past.

Steve Glaser, VP of corporate marketing and business development at Verisity, said his company became a SystemVerilog provider with its acquisition of Axis Systems. "We want to make sure as we move down the path that we're doing this in a way that's consistent with the rest of the industry, and we don't repeat the mistakes made with Verilog 2001," he said.

Glaser noted, however, that Verisity is supporting only the design and assertion constructs in SystemVerilog. Verisity's "e" language competes with the testbench portions of SystemVerilog. "We believe there are multiple alternatives in the testbench space," he said.

Victor Berman, group director of language standards at Cadence, said it's important that any SystemVerilog constructs have broad industry support. "It's important for adoption that there be a timeline," he said. "There could be a delay of several years if there isn't organized coordination."

Berman said Cadence intends to implement the testbench portions of SystemVerilog as well, but wants to concentrate on the "highest priority" items first.

As for Synopsys, Glaser said "we hope they participate with us, and that whatever they do, they use the interoperability test suites we come up with in this group." No one expects Synopsys or any other vendor to slow down their existing implementation plans, Glaser said.

Accellera versus the IEEE

While the new coalition seeks greater harmony in implementing SystemVerilog, a language split is possible if Accellera doesn't take SystemVerilog 3.1a to the IEEE 1364 committee, some observers said.

Sutherland noted that some members of the Accellera board of directors don't want to go to the IEEE 1364 group, because the chairman, Mike McNamara, is Verisity's CTO. The IEEE 1364 group has clashed with Accellera in the past, calling for Accellera to donate SystemVerilog over a year ago and then forging ahead with its own plans for Verilog 2005.

Going to a different IEEE group is a "very bad idea," Sutherland said. "SystemVerilog is not a standalone standard, it's simply a set of extensions to Verilog. If you can't keep the extensions synchronous with the evolution of the standard, those extensions become worthless."

Berman, who is vice chair of the IEEE Design Automation Standards Committee (DASC) and an Accellera director, said some members of the Accellera board want to turn SystemVerilog 3.1a over to a separate "corporate entity" group within the IEEE distinct from the DASC and IEEE 1364. He said the decision is not finalized but will probably be made early next week (May 17, 2004).

"My personal feeling is that it would be mistake that could lead to a bifurcating of the languages," he said. "It will be a real mistake for the industry if a separate working group works on one part of the language while 1364 works on the base part of the language."

Brophy refused to comment on Accellera's plans with respect to the 1364 working group. "We are committed to a path into the IEEE," he said. "Accellera has not come to a conclusion to issue any statements to the press."

- Richard Goering

EE Times

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