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Lighthouse introduces synthesis tools for Verilog test

Posted: 19 May 2004 ?? ?Print Version ?Bookmark and Share

Keywords:lighthouse design automation? synthesize? verilog? testbenches?

Promising to reduce testbench development time by up to 80 percent, startup Lighthouse Design Automation Inc. will introduce tools that synthesize Verilog testbenches from high-level specifications. Lighthouse calls its inFact tool set the first "intelligent" automatic testbench sequence generator.

Lighthouse has targeted a key area, given that functional verification can take up to 70 percent of a chip design flow. The Lake Oswego, Oregon, company appears to be offering portions of what Gartner Dataquest Inc. calls the "intelligent testbench," a crucial enabler for nanometer-scale ICs, and to be forging some new ground in electronic system-level (ESL) verification.

Originally launched as Silicon Forest Research, Lighthouse is emerging from several years of "very aggressive research" in verification, said president and CEO Clifton Lyons. The company now has a production-ready product and several customers, including Fujitsu, Hitachi, Mentor Graphics' intellectual-property (IP) division and SanDisk, he said.

"Our mission is to dramatically improve functional verification," said Lyons. "We didn't want to just do an evolutionary 10 percent improvement, but a whole new approach that would allow us to improve it by a factor of 10 and at the same time make it easy to adopt for people who are new to it."

Lyons is a former director of engineering at Mentor Graphics Corp. and was a founder of Performance CAD. Sudhir Kadkade, Lighthouse's chief technology officer, led the engineering team that produced the widely used Verilog-XL simulator when he was at Cadence Design Systems Inc. Mark Olen, VP of sales and marketing, previously worked for Mentor, Teradyne Inc. and Cascade Microtech Inc.

Lighthouse's inFact Intelligent Compiler (iComp) compiles a C++ specification that describes a design's behavior, and synthesizes executable sequence generators that adaptively construct sequences of transactions during simulation. The run-time environment, iSync, manages the interaction between one or more sequence generators during simulation. Lighthouse also offers iGen, a library of synthesized engines for standard interfaces, and iSpec, a utility for building custom interfaces.

The company claims to be offering unique, nondeterministic technology that combines elements of formal verification and functional simulation. "The programming approaches done in the past make it impossible to add a sufficient level of intelligence to the system," said. "So we took an automata-based approach using Backus-Naur Form [BNF] that allows us to take a very abstract description from the user [of] what the design is capable of doing."

Users write BNF specifications in C++, he noted, so there's no need to learn a specialized language. Most engineers have had some training in BNF in school, Lyons observed.

While automata-based approaches are nothing new, Lighthouse has developed a patent-pending technology it calls "self-adapting nondeterministic automata."

"Our automata are self-adapting, so they morph as the simulation runs," Lyons said.

Lighthouse also has patents pending on its "intelligent graph traversal" technology, which constructs spatially distributed sequences of transactions during functional simulation, and its dynamic resource schedule manager, which lets multiple sequence generators run in parallel while making best use of limited resources like DMA channels.

The result of all this, said Lyons, is more efficient and effective testbenches. In a customer case study at SanDisk Corp., he said, inFact produced a testbench with 2,500 lines, compared with 13,000 lines when using Verilog. The inFact testbench ran three times faster and found 26 bugs, while the Verilog testbench found only six bugs.

Lighthouse also has an advantage over hardware verification languages, said Olen. HVLs use a pseudorandom approach, which still requires users to think in terms of sequence structures, he said. "Our tool, instead, allows the user to focus on the specification. And rather than pseudorandom, we use a spatially distributed algorithm that ensures we don't replicate sequences that happen during a pseudorandom approach."

Another unique capability, Olen said, is inFact's ability to take a number of module-level testbenches, including existing testbenches that come with IP blocks, and put them together at the system level and reuse them.

The input to inFact consists of both specifications and tests. Users can place assertions into the BNF C code or into the Verilog design. The output is a C++ testbench with a Verilog wrapper, along with graphs that can be compared with the original specification. The tools support SystemVerilog 3.1, and testbenches should work with any standard Verilog simulator, Lyons said.

While both the compiler and run-time environment are needed, they're licensed separately because users might have one iComp license for every five iSync licenses, Lyons said. For its part, iGen includes executable engines for interfaces such as PCI, PCI-X and Ethernet, while iSpec is an ASCII file that lets users build a custom interface.

The inFact suite is available today with pricing beginning at $17,400 for a one-year license.

- Richard Goering

EE Times

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