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Synopsys releases design platform upgrade

Posted: 24 May 2004 ?? ?Print Version ?Bookmark and Share

Keywords:synopsys? design platform? galaxy 2004?

Synopsys Inc. has launched an upgrade to its complete design platform that delivers across-the-board improvements in run-time, capacity, quality-of-results (QoR), silicon technology support and turn-around time.

"The vast range of advancements in Galaxy 2004 demonstrates the tremendous rate at which Synopsys is innovating to produce the most convergent flow for SoC design," said chairman and CEO Aart de Geus. "Galaxy 2004 represents a big step forward in design technology, providing the fastest path to the best results, which are highly correlated to silicon."

According to Synopsys, numerous innovations in Galaxy 2004 contribute to significant performance improvements throughout the entire flow. Design Compiler 2004 posts two times faster run-time, 40 percent better capacity and 10 percent better area QoR than last year's release. It now also supports SystemVerilog and a new VHDL Compiler that is five times faster and has broader language coverage than its predecessor.

Advancements have been made to improve timing correlation throughout all stages of the implementation flow and the industry-standard sign-off tools - PrimeTime and Star-RCXT. All tools in the Galaxy platform now use identical constraints, libraries and delay calculation to facilitate rapid design convergence.

The JupiterXT design planning solution in the Galaxy 2004 has also been greatly enhanced, with twice the capacity of last year's version and up to three times speed improvement in time required to create a detailed floorplan. The design solution now also features a fast feasibility mode, a completely new automatic macro placement capability based on Synopsys' patented placement technology, power plan synthesis, and a highly predictive capability for power network analysis (PNA).

The PNA capability enables IR-drop analysis at the floorplan level with high correlation to final IR-drop sign-off in Astro-Rail. This solution also drives PrimeTime SI to enable voltage-drop dependent timing sign-off.

In the Physical Design area, both Physical Compiler and Astro have been improved. Physical Compiler now has two times faster run-time, two times better capacity and 15 percent better timing QoR than last year's version. It now also includes a new Distributed Physical Synthesis capability, which distributes large flat designs over multiple CPUs for fast turn-around time, and performs a final global optimization for best quality of results.

Astro now has 50 percent better capacity, TCL command-line support, simpler library preparation and a new methodology that achieves high QoR without complex scripting. In physical verification, Hercules Physical Verification Suite (PVS) now has two times faster runtime, distributed processing that delivers an additional five times faster turn-around on six CPUs, and foundry-qualified optimized runsets available from all major foundries.

In the testability area, DFT Compiler is now two to five times faster, has two times the capacity and features timing-based physical scan ordering in Physical Compiler. TetraMAX ATPG is now two to three times faster, produces three times fewer test patterns, and now fully automates Phase-Locked Loops (PLLs) and internal clock control to provide a complete solution for at-speed testing.

The 2004.06 version of Galaxy Design Platform is expected to be made available to customers via two releases in June and July of 2004.

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