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STATS expands turnkey solutions with DFT capabilities

Posted: 25 May 2004 ?? ?Print Version ?Bookmark and Share

Keywords:st assembly test services? stats? design-for-test? dft? scan insertion?

ST Assembly Test Services Ltd (STATS), an independent semiconductor test and advanced packaging service provider, has expanded its integrated turnkey solutions with Design-for-Test (DFT) capabilities that will assist customers in improving testability and throughput of their devices for a lower cost of test and faster time-to-market.

"With the industry trend heading towards more complex and higher pin count devices, test is fast becoming a significant part of total manufacturing cost," said Jean Emmanuel Perdereau, worldwide VP for Test. "As a result more semiconductor companies will turn to DFT to lower cost of test, simplify test processes as well as shorten debug cycles and improve time-to-market. It is also increasingly critical for companies to move package design and selection, thermal and electrical simulation, and test planning upstream in the product design cycle."

As part of its DFT capabilities, the company will provide consultation and technical training to share the advantage of deploying DFT and various DFT techniques including Scan Insertion and Automatic Test Pattern Generation (ATPG), Built-In-Self-Test and Boundary Scan (JTAG).

At the initial design stage, STATS will offer consultation on DFT implementation, selection of DFT techniques for optimizing test efficiency and reducing test vector set. At the test stage, it will engage with customers on test design, verification, vector generation, and test program creation.

Customers can also tap into the third party links STATS has formed with other EDA providers and Automatic Test Equipment (ATE) suppliers. These links are targeted at helping customers ease the costs of DFT tools, keep abreast of changing ATE parameters for DFT as well as reduce ATE configuration requirements.





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