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Altera Nios II delivers over 200 DMIPS

Posted: 24 May 2004 ?? ?Print Version ?Bookmark and Share

Keywords:nios ii? processor? altera? stratix ii? cyclone?

Packaged by the company as a "perfect-fit" processor, the second generation soft processor from Altera Corp. delivers over 200 DMIPS of performance when combined with the company's Stratix and Cyclone series of FPGAs, and the HardCopy structured ASIC family.

The original Nios was launched in 2000. Since its release, more than 13,000 Nios development kits have been shipped. "Nios II is just not an upgrade of the original Nios," said Louie Leung, Marketing Director for Asia-Pacific. "It is an evolution."

The Nios II family is built on a completely new architecture. It consumes, on average, 50 percent fewer FPGA resources, yet doubles computational performance compared to the first generation.

The new RISC processor can be used in applications that require a general-purpose, 32-bit embedded microprocessor. According to Altera, the Nios II devices feature unlimited peripheral options, custom data paths, multi-processor systems, custom instructions, and high bandwidth switch fabric.

The embedded processor supports 256 custom instructions with fixed or variable clock-cycle operations that designers can use to accelerate time-critical sections of code. These custom instructions allow designers to implement compute-intensive algorithms in hardware and "call" them in software just like a C-language subroutine.

Using Nios II in FPGAs allows for the hardware block to be customized. "This gives customers control on how they want to make this hardware block," said Leung.

A Nios core for everyone

With the newly released solution, customers can chose the size and performance of their core, select their FPGA based on cost and performance requirements, implement multiple processor cores, and accelerate instructions in hardware. "Aside from flexibility, the other benefit of the Nios II is the SoPC integration," adds Leung.

The Nios II family consists of three members - fast, economy and standard - one for maximum system performance, one optimized for minimum logic usage, and one that strikes a balance between the two. The three cores use the same instruction set architecture (ISA) and are 100 percent binary code compatible, letting designers change CPUs as their system requirements change without affecting their existing software investment.

The company said that standards-based solutions are subject to obsolescence as systems become more advanced, whereas Nios II processor-based solutions avoid obsolescence because they are constructed from HDL code that can be retargeted to address new system requirements.

The family of processors uses the Avalon switch fabric, which enables multiple data transactions for unmatched system throughput performance. The switch fabric provides a set of pre-defined signal types with which a user can connect any number of more than 60 available peripherals.

The Nios II processors are supported by the Nios II integrated development environment (IDE), a complete set of robust development tools for software engineers. It is based on the open and extensible Eclipse platform to combine a common user interface with best-in-class environment and seamless integration with third-party tools.

Production of the Nios II family of devices is scheduled for Q2 of 2004.

Margarette Teodosio

Electronic Engineering Times - Asia





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