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Tech coalition develops ultra-thin CMOS process technology

Posted: 31 May 2004 ?? ?Print Version ?Bookmark and Share

Keywords:stmicro? cea-leti? AIXTRON develop process for CMOS transistors?

STMicroelectronics, CEA-Leti and Aixtron have developed an advanced process technology for the creation of ultra-thin transistor-gate-insulation layers for low-power applications at the 65nm and 45nm CMOS transistor technology nodes. The new process is anticipated to reduce transistor leakage current by the deposition of 'high-k' gate-insulation material.

The process, called AVD (atomic vapor deposition), has demonstrated equivalent oxide thickness (EOT) values of 1.15nm or 11.5 Angstroms based on hafnium dioxide/silicon dioxide/silicon (HfO(2)/SiO(2)/Si) stacks offering leakage current densities as low as J(L)=6.8x10-2A/cm2 at 1.5V.

The results were obtained by the advanced modules team of researchers from STMicro and CEA-Leti at STMicro's Crolles facility using a Tricent Aixtron 200/300mm bridge cluster tool. The HfO2 deposited layer process was developed in conjunction with Aixtron, and the wafer processing and the characterization were performed at CEA-LETI facilities in Grenoble.

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