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Adveda launches extension to RTL simulator

Posted: 01 Jun 2004 ?? ?Print Version ?Bookmark and Share

Keywords:adveda b.v.? adveda? rtl simulator? systemc wrapper? pli/fmi wrapper?

Adveda B.V. has introduced its Univers Modeler, an extension to its RTL simulator, which generates a SystemC wrapper or a PLI/FMI wrapper around a native simulation model, compiled within the simulator. According to Adveda, this allows users up to 100 times faster simulation speeds within their own simulation environment through its PLI, FMI or SystemC interface.

The Univers Modeler takes the original RTL-code and converts it automatically to a cycle-accurate simulation model at a higher level of abstraction, wrapped in SystemC. The generated model runs faster than an RTL simulation, similar to the speed reached with manually-written SystemC models.

"A growing number of designers are looking at SystemC modeling as a way to speed up their verification process," said CEO Cor Schepens. "With the Univers Modeler, designers can take immediate advantage of fast SystemC models without any change in their design flow."

IP vendors can also take advantage of the newly-developed extension. "IP vendors will benefit from the fact that the fast simulation models are also optimally encrypted, leaving them the option to determine the internal signals which are visible for the end-user," Schepens added.

With Univers Modeler, designers can save months of writing models by hand. It also guarantees correct functional and cycle-accurate behavior, allowing designers to debug their real RTL design rather than just a model of the design. It can also wrap these models with a PLI or FMI interface, allowing the models to be used within existing RTL simulators. The extension handles the full synthesizable RTL syntax, including multiple asynchronous clocks, asynchronous resets and tri-state signals. The first production release will support the VHDL RTL language, and is available immediately.

The company said that the Univers hardware software co-verification solution combines fast hardware simulation and fast Instruction Set Simulators (ISS) using a unique architecture, which employs only one simulation kernel in a unified development environment.





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