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For metrology, nano changes everything

Posted: 01 Jun 2004 ?? ?Print Version ?Bookmark and Share

Keywords:metrology? ic? gate? semiconductor? transistor?

Diebold: Two interesting aspects to future measurement needs are feature size and number.

One can classify the characterization and metrology requirements for ICs beyond the 65nm node as the measurement of nanoelectronics. Two interesting aspects to future measurement needs are feature size and number.

According to the International Technology Roadmap for Semiconductors, the transistor gate length of microprocessors at the 45nm node will be less than 20nm in 2010 and will shrink to less than 10nm for the 22nm node in 2016. A memory device at the 45nm node will have about 1.7 billion transistors; a logic device will have slightly more than 300 million transistors.

Thus, in-line metrology must provide process control for nanofeatures with statistically significant precision at an atomic level. And materials characterization must provide information from atomic dimensions.

For example, future transistors will be built from high-dielectric-constant replacements for silicon dioxide and will use metal gate electrodes instead of doped polysilicon. New transistor designs being explored include multiple gates, FinFETs and CMOS on ultrathin strained silicon-on-insulator (SOI) substrates.

This complicates metrology development. For example, optical measurement of high-k on strained SOI involves additional reflections that might degrade the atomic-level precision required for process control.

We must also determine the optical constants vs. wavelength (dielectric function) for at least the high-k and ultrathin strained-silicon layers of the stack. The new structures bring the potential need to move from measuring horizontal films to vertical films. Adding the metal gate brings the potential need to measure the gate dielectric under the metal gate.

Metrology R&D is working on these issues and exploring the possible use of clustered metrology stations in the deposition systems that fabricate the high-k and metal gate without breaking the vacuum. Electrical metrology becomes increasingly important as film stacks grow more complicated.

Once the transistors are fabricated, gate length must be verified. That leads to a conundrum: the most prevalent metrology for critical-dimension (CD) measurement is CD-SEM, which measures a single value from the local distribution of CD values. What we really need is the average value and width of the local distribution. Attaining this information across the wafer and from wafer to wafer provides the global statistics of CD values required for process control.

Another aspect is the use of advanced process and equipment control to link processes and tighten the distribution of CD values. Scatterometry quickly provides the average value of the local distribution but not the distribution width. With no perfect method at hand, metrology R&D for CD emphasizes extending both technologies.

Now we can peer into the metrology and characterization connections between nanoelectronics and nanotechnology. To be profitable, nanotechnology must be manufactured in huge numbers. Thus, manufacturing process control may need to measure how nanofeatures are changing, instead of seeing the nanofeatures on each device. We'll also need to characterize nanodot- and nanowire-sized features. (The transistor channel region of CMOS built on ultrathin strained SOI is itself nanowire-like.)

Nanoelectronics and the rest of nanotechnology can use 3D atomic maps. The next generation of transmission electron microscopes (TEMs) will have electron lens technology that corrects for lens aberrations, which will push the resolution limits of TEM and associated spectroscopy further below 0.1nm. Also, the atomic mapping capability of the local electrode atom probe is intriguing, and may be further developed.

- Alain Diebold

International Sematech

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