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Synplicity spins Xilinx-specific version of RTL debugger

Posted: 01 Jun 2004 ?? ?Print Version ?Bookmark and Share

Keywords:debugger? debug? rtl? fpga? asic?

Synplicity Inc. has released a version of its Identify RTL debugging software with features targeting users of Xilinx Inc.'s FPGAs. The company has also launched a new version of Certify, its ASIC-prototyping software, that supports the Solaris 64bit operating system. In addition, White Eagle Systems Technology Inc. has joined its Partners in Prototyping Program, Synplicity said.

Brian Caslis, director of marketing for verification products at Synplicity, said ver 2.0 of Identify features an incremental debugging flow for Xilinx FPGAs that allows designers to first debug specific signals in their hardware and then change those signals quickly.

Today's hardware-debugging tools force designers to run multiple iterations of synthesis and debug insertion if they don't find the problem they are looking for, Caslis said. This occurs because it is difficult for a designer to find errors in the post-place-and-route netlist, often because signal names have changed and it is hard to associate them with the original RTL source. Because a designer is forced to resynthesize a design and go through place-and-route again, several hours are added to every debug iteration.

With Identify 2.0's support for RTL incremental flows, signals for incremental debug are automatically correlated back to the original RTL source code, so users don't have to spend time finding the origin of a bug, Caslis said. Users who want to view signals can open Identify's "instrumentor" utility and request that the tool perform an incremental debug session.

A few seconds

Instead of synthesizing the design again, the incremental debug session loads the original debug session, queries a database file and correlates the signals in the design to the place-and-route files - typically in just a few seconds, said Caslis.

Once that's done, the tool displays the RTL source code, showing the signals it can correlate between the RTL and back-end database files.

Caslis said that Synplicity correlated the technology with Xilinx's native place-and-route software. Close support from other programmable-logic vendors will be available in future releases, he said.

Ver 2.0 also includes a multiple-sample clock feature that allows designers to deal with multiple asynchronous clock regions in a single debugger window. Previous versions of the tool required users to track debugging through multiple copies of a debugger window, Caslis said.

"Now, within a single debugger window, you can specify the multiclock feature or multiple logic analyzer elements to have multiple sample clocks in different parts of the design. This allows you to deal with large asynchronous systems and be able to sample or look into anything you want to inside of them," he said.

Users can run multiple simple triggers at once or create complex state machine equations for sequential events to debug designs. With the multiple-clock feature, "you can have one sample region trigger out to another sample region, extending the triggering capability even more," said Caslis. "The benefit here is being able to do much more complex debug more easily than before."

Caslis said a project-management feature inside the instrumentor and debugger engines' user interfaces makes it easier to load projects and data directly into the software.

Identify 2.0, which runs on Linux 7.2, 7.3 and 8.0 as well as Windows 2000 and XP Professional platforms, starts at $9,000 for a one-year, single-vendor time-based license. Users of the Xilinx ISE design environment have access to a promotional software license of Synplicity's Identify Lite software until August 31.

Synplicity has also released a version of Certify that supports the 64bit Solaris OS. That support will allow users to synthesize prototypes as large as 10 million gates or larger in a single pass without having to break up the design into smaller pieces, Caslis said.

Pricing for the Certify 6.4 software starts at $45,000 for a one-year time-based license.

The company has added White Eagle Systems to its Partners in Prototyping Program. White Eagle has delivered a unique methodology for building FPGA-based prototypes, Synplicity said. The San Jose company's Scallopwing standard configuration contains four Xilinx XC2V8000 Virtex-II devices with 32 million gates of programmable logic.

Synplicity also announced two patents that cover the way its debugging technology enables designs implemented in FPGA hardware to be debugged using original RTL source code.

- Michael Santarini

EE Times

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