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Optimizer vows custom speed for standard blocks

Posted: 01 Jun 2004 ?? ?Print Version ?Bookmark and Share

Keywords:optimizer? eda? spice? tool? synthesis?

EDA startup Zenasis Technologies Inc. promises designers custom performance out of a standard-cell flow with the latest version of its ZenTime cell-based timing-optimization tool.

A 2002 startup, Zenasis quietly released ZenTime in May 2003. Five big customers, their names still undisclosed, have since adopted the tool, using it to obtain optimal timing from critical blocks, said Rob Roy, vice president of marketing and business development.

When ZenTime examines a design, it first seeks to optimize its timing, said Vamsi Boppana, a co-founder and now the vice president of Zenasis. "It looks at the design, identifies chunks of logic that can be re-implemented at the transistor level, does an implementation in an optimal way and outputs an optimized design."

Boppana said he expects ZenTime to be used after physical synthesis is completed. The optimization tool accepts any standard output of synthesis tools, such as the .lib and DEF formats, BSIM models or a Verilog netlist.

With guidance from users, ZenTime can analyze blocks of up to 600,000 gates, locate timing-critical areas and abstract logic to basic Boolean forms. The Boolean data is then re-mapped to the transistor level using proprietary incremental mapping and placement engines. ZenTime generates additional library elements and outputs a design in the same standard formats that went into the tool.

ZenTime has several internal analysis engines to assist with optimizations. Analysis is aided by a built-in SPICE engine that is 40 to 50 times faster than standard SPICE simulation, the company said.

ZenTime groups small elements into a proprietary macrocell called a Zen cell, Boppana said. Complex functions are largely done under the hood, with algorithms developed by Zenasis, so that users are working with familiar physical synthesis and placement instructions, he said.

"What is on the inside of the tool is very complex, but we have made every effort to make it look like it isn't a complicated tool from a user perspective," said Boppana. "It has the usual EDA interfaces like TCL. Anyone using an automated synthesis place-and-route flow will find the commands familiar."

Designs using the tool will see an average performance improvement of 15 percent, according to Zenasis. The company showed benchmark data indicating the clock rate of an ARM 966 core jumped 16 percent, from 297MHz up to 345MHz, after running through ZenTime. Similarly, the company claimed that a MIPS processor core showed an 11 percent improvement, going from 250MHz to 277MHz after running through ZenTime.

Roy said ver 2.1 of the tool, available this month, improves runtime threefold. The new version no longer requires that designers rerun the tool in placement to ensure legal optimization, as the company has ensured all optimizations are placement-legal.

The revision also boasts integrated netlist and placement optimization as well as support for multiple clock domains. ZenTime also supports commonly encountered latched-based designs, the company said, and its improved transistor mapper aids overall implementation quality.

A term-based license for ZenTime is priced at $195,000 per year. The software will run on Linux and Sun Solaris platforms, Zenasis said.

- Michael Santarini

EE Times

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