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Cadence supports Virage Logic ASIC design libraries

Posted: 04 Jun 2004 ?? ?Print Version ?Bookmark and Share

Keywords:cadence design systems? virage logic? asap? logic structured-asic? metal programmable?

Cadence Design Systems Inc. is supporting Virage Logic Corp.'s area, speed and power (ASAP) Logic structured-ASIC metal programmable and standard cell libraries within the its Encounter digital IC design platform.

The move is expected to leverage the capabilities of SoC Encounter's IC implementation in the structured array, as well as standard cell markets. Further, it enables mutual customers to make trade-offs between density, cost and performance according to their requirements. At present, this capability is deployed with SoC Encounter 3.3.

Adam Kablanian, president and CEO of Virage Logic, said, "The large installed base of SoC Encounter users now has the flexibility of mixing and matching our metal programmable and standard cell libraries on the same design to achieve maximum savings in overall chip costs."

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