Atrenta releases RTL checker

Atrenta Inc. has released an assertion-based functional analysis tool that checks whether user RTL is functionally correct and fixes problems to minimize iterations between simulation and synthesis.

The new tool, called Periscope, uses an assertion-based verification engine for functional analysis, advanced functional algorithms and clock domain crossing (CDC) analysis engines.

Periscope's CDC engine automatically detects and reports missing or incorrect synchronizers. It also detects other clocking problems such as improper encoding of multibit CDC signals, reconvergent signals and hold-time issues for fast-to-slow clock crossings. The company claims the CDC analysis portion of the tool can be used for an entire chip design.

In addition to CDC analysis, Periscope uses a combination of formal techniques and simulation to check for problems such as bus contention, control bus synchronization, uninitialized memory and simultaneous set/reset, Atrenta said.

The tool also provides functional verification of finite state machines, including search for unreachable states, deadlock states and inactive state transitions. It can also detect dead code and functionally validate tristate busses and case statements, the company claimed.

The tool also supports the Accellera standard open verification library assertions, including FIFO overflow and underflow, handshaking checks and range checks. The Periscope platform will also enable support for other popular assertion languages, such as PSL, which Atrenta plans to provide in the near future.

Pricing for Periscope starts at $50,000 for a single time-based license.

- Mike Santarini

EE Times