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0-In tools support Accellera SystemVerilog 3.1a

Posted: 08 Jun 2004 ?? ?Print Version ?Bookmark and Share

Keywords:0-in design automation? archer verification system? accellera? systemverilog 3.1a? property specification language?

0-In Design Automation Inc., an assertion-based verification company, has announced products within its Archer Verification system that provide support for Accellera's SystemVerilog 3.1a design constructs and IEEE-1076 VHDL.

The new products join 0-In's support of standard languages that include IEEE-1364 Verilog and Accellera's Property Specification Language (PSL). President and CEO Steve White said, "Now customers using SystemVerilog and VHDL will have access to the industry's most widely used tools and proven methodologies for reaching verification closure."

Archer-CDV will support SystemVerilog 3.1a design constructs and VHDL to provide structural and assertion-based coverage capabilities within a coverage-driven verification methodology. It leverages the company's CheckerWare library of assertions and monitors to detect bugs earlier and make debug faster. CheckerWare encapsulates both functional checking and structural coverage monitoring for testing common design elements and standard interfaces.

Archer-SF will support VHDL to provide design teams with an easy-to-use, powerful static assertion-based and formal verification capability for finding bugs. It includes automatic RTL rule checking, static clock-domain crossing verification and static formal verification of assertions.

The Archer-CDV has a North American list price of $50,000 and the Archer-SF has a list price of $60,000, both for a one-year time-based license. Both are already available for early-access customers and will be generally available in the Q4.

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