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TSMC Reference Flow 5.0 includes Optimal tools

Posted: 07 Jun 2004 ?? ?Print Version ?Bookmark and Share

Keywords:optimal? tsmc? reference flow 5.0? powergrid-dc? paksi-e?

The Reference Flow 5.0 from TSMC addresses two nanometer integrity issues that are observed at both the IC and package design levels - power closure and timing closure. According to TSMC, it recognizes the need for power-aware, integrated IC and package design.

"As we geared up to handle the next-generation of system-on-chip (SoC) designs, it became clear that power closure would become a dominant technical issue," said Genda Hu, VP of marketing at TSMC. "The ability to provide power closure through to the package design increases the reliability of the design, greatly enhances the design experience and accelerates time-to-market."

A key player in the integrated chip and package co-design methodology, Optimal Corp. contributed three tools to the Reference Flow 5.0.

Optimal cofounder and CTO Dr. An-Yu Kuo said, "As wireless communications and consumer end products begin requiring higher and higher current or speed, power and timing closure become essential for time-to-market requirements."

Optimal's three tools

The codeveloped methodology includes Optimal's PowerGrid-DC that provides the IR drop and current density, and the PakSi-E and SIDEA.

In the past, the current entering a semiconductor device was relatively low so the resistance created by a chip's package (IR drop) was easily approximated and dealt with through package and lead selection. Today, design team must contend with currents as high as 200A. In this environment, a package resistance as small as 0.1-milliohm can cause 20mV of voltage drop, enough to upset a 1V design.

The PowerGrid-DC provides an equivalent resistive SPICE netlist among the solder bumps (or bondwires) and solder balls. This SPICE netlist is imported as a loading condition into third-party on-chip tools to perform IR drop analysis. The interaction between the chip and package is then accounted for automatically.

Due to the space constraints, the signal trace routing on a package tends to have multiple lengths. For example, the signal traces routed to the corner of a package are usually longer than those routed to the edge of a package. Such differences among the trace lengths need to be compensated for on the PCB. An automated design flow is needed to quantify the timing delay from the I/O circuitry to the package pins (so that proper trace compensation can be made on PCB).

Users of the Reference Flow 5.0 methodology can codesign their IC and package by using the PakSi-E and SIDEA to extract the package parasitics and generate timing information in standard delay format (SDF). This information is provided as a loading condition to the third-party on-chip tools that extract the I/O circuitry and redistribution layer parasitics, and perform the static timing analysis, all the way from chip I/O to the package pins (or solder balls). Such IC and package codesign allows the system or board designers to automate the routing adjustment on PCB.

The PowerGrid, PakSi-E and SIDEA are available immediately on Microsoft Windows. List price starts at $35,000 per license.

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