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Silvaco rollout includes mixed-signal simulation

Posted: 10 Jun 2004 ?? ?Print Version ?Bookmark and Share

Keywords:silvaco international? 41st design automation conference? simulator? rc extractor? inductance extractor?

Silvaco International will come to the 41st Design Automation Conference with a new mixed-signal simulator, a full-chip RC extractor, a harmonic-balance simulator, an inductance extractor and a soft-error modeling tool. The products will support Linux under a new graphical user interface.

CEO Ivan Pesic described the Harmony-AMS simulator as a "flagship" product. Silvaco, whose SmartSpice analog simulator claims some 8,000 design seats, recently bought Simucad Inc. and its Silos-AMS mixed-signal simulator. The new product is a result of that marriage. "We architected a single-kernel mixed-signal product," Pesic said. "The analog side is the master of the clock. The digital side is integrated internally as a dynamically linked library."

As a result, he said, Harmony-AMS doesn't lose accuracy on the analog side, and offers a single viewing environment in which analog and digital signals are presented on the same time scale. It's aimed at applications with lots of analog functionality and moderate digital functionality, yet is able to handle digital blocks of up to 500,000 gates, Pesic said. It supports IEEE 1364-2001 Verilog as well as the Accellera 2.1 Verilog-AMS standard. It's available now for $80,000 on Linux, Windows and Sun platforms.

Harmonic balance

Silvaco's SmartSpice-RF harmonic-balance simulator, meanwhile, provides frequency-domain, steady-state, large-signal analysis of nonlinear circuits driven with multitone sources. It performs periodic and quasiperiodic steady-state analyses for large-signal and small-signal applications, each with full parametric sweep and Monte Carlo control parameters.

Pesic said the tool's functionality is comparable to Agilent Technologies' widely used ADS simulator. SmartSpice-RF, which starts at $60,000, also works with Silvaco's IC physical-design flow.

Also aimed at RF designers is Quest, a high-frequency parasitic extractor. It calculates 3D frequency-dependent inductance, resistance, capacitance and capacitive loss for multiport networks for RF Spice analysis. Quest creates W-element transmission lines, multiport S-parameters and spiral-inductor Spice models from GDSII layouts.

"This is the first time you can get measured data and convert it into W-elements and input it into Spice," Pesic said.

Silvaco claims "3D accurate" full-chip resistance and capacitance (RC) extraction for another new product, Hipex. It's based on the same Digital Equipment Corp. technology that was used to build Simplex extraction products, according to Pesic.

Using a geometric algorithm based on trapezoids, Hipex is not a true 3D field solver, said Ken Brock, Silvaco's VP of marketing. However, he noted, Hipex uses resistance and capacitance models built with Silvaco's 3D field solvers. Additionally, Hipex lets users write their own equations and create their own models, which can be characterized with a 3D field solver, he said. Through Hipex's "selected net" feature, users can pick a particular set of nets using Silvaco's Expert layout editor and run extraction only on those nets, he said. Hipex can also work with other vendors' layout products, since it outputs Spice files and uses standard formats.

Capacitance extraction includes parasitic overlap, lateral and fringe. Resistance extraction includes parasitics for lines, contacts and vias, and it splits long conducting tracks for more-accurate RC distribution. Users can trade off accuracy vs. run-time. Users can purchase Hipex-C for capacitance, Hipex-RC for resistance and capacitance, or Hipex-CRC for network reduction. All are now available on Linux, Windows and Sun platforms, starting at $80,000 for Hipex-RC for a term-based license.

Finally, Silvaco has integrated the Atlas 2D/3D Single Event Effects (SEE) module and the SmartSpice-SEE module with Hipex and with Silvaco's HyperFault simulator to provide a complete flow to identify SEEs-also called soft errors-in analog, digital and mixed-signal designs. They are related to the effects of cosmic rays, alpha particles and neutrons.

"At 90nm, radiation kills the chip. We're releasing a solution from the T-CAD market into SmartSpice, so that people can figure out where problems are going to arise," Pesic said, referring to Silvaco's origins in the technology-CAD sector.

A complete SEE solution starts at $500,000 for a term-based license.

- Richard Goering

EE Times

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