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EDA user study puts Synopsys in top spot

Posted: 09 Jun 2004 ?? ?Print Version ?Bookmark and Share

Keywords:ic design? synopsys? mentor graphics?

IC design starts are up over last year. Ninety-nanometer is becoming a target process node for designers. Novas Software Inc. ranked first among vendors in terms of customer satisfaction. And Synopsys Inc. took more top honors than any other supplier.

Those are just some of the highlights of this year's EE Times IC EDA user study, which is being released at the Design Automation Conference June 8, 2004.

EE Times user surveys collect data on EDA tool usage and preferences in North America and Europe. This year, a total of 1,503 respondents replied to three separate surveys: IC design, FPGA design and PCB design.

Fifty-three percent of the 662 respondents to the IC survey called themselves design and verification engineers; 28 percent were in engineering management; 7 percent in general and corporate management; and 11 percent were "other."

Forty-four percent of respondents came from companies with annual revenues in excess of a billion dollars. Thirty-five percent worked at fabless IC companies; 21 percent at integrated device manufacturers; 20 percent at systems companies; and the remainder came from intellectual-property providers, design consultancies, foundries or other operations.

The median gate count for IC design projects doubled from 1 million gates in 2003 to 2 million gates this year, said the study. Twenty percent of the 553 respondents said their latest design projects involved 10 million or more gates.

The most targeted process node of current projects is 0.13?m, according to the study. Thirty-eight percent of those surveyed said their latest projects target the 0.13?m node; 19 percent are aiming for the 90nm node; and 4 percent are targeting nodes below 90nm. Eight percent are targeting 0.50?m; 6 percent are at 0.35?m; 4 percent at 0.25?m; 18 percent at 0.18?m; and 3 percent at 0.15?m.

Thirty-four percent said there will be "more" design starts in 2004 than in 2003 at their company. Twenty-seven percent said there will be "much more"; 29 percent said there will be the same amount; while 7 percent said there will be "less" design. Three percent said there would be "much less."

According to the survey, the average length of a design project increased to 40 weeks in 2004, up from 32 weeks in 2003.

Readers said the "most critical" issue and challenge in chip-level design is the accuracy and integrity of design tools, followed by timing closure; tools' ability to handle complex designs; functional verification; models and libraries; meeting realistic cost targets; signal integrity; and analog mixed-signal.

Readers ranked the top five most important issues in selecting a chip vendor, in descending order, as: best after-sales support; competitive pricing; technology leadership; technology leadership three years from now; and support of open standards.

Novas Software repeated as the winner of the customer satisfaction category, followed by Synopsys, Mentor Graphics, Nassda and Synplicity.

Synopsys took more top honors than any other company in this year's survey in such categories as vendor perception; best training service; well-managed company; best documentation; and most ethical.

But Cadence Design Systems Inc., which has been regrouping over the last year, is gaining ground on Synopsys in the survey rankings. Among those surveyed in Europe, respondents ranked Cadence higher than Synopsys in several categories. And where Synopsys ranked first, Cadence placed second in most of the categories.

- Mike Santarini

EE Times

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