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Mentor, Cadence share most top honors in PCB study

Posted: 10 Jun 2004 ?? ?Print Version ?Bookmark and Share

Keywords:pcb? eda? ic? fpga?

Mentor Graphics and Cadence Design Systems took the lion's share of top honors in a PCB EDA survey, but Agilent EEsof garnered the top spot in customer satisfaction.

The 2004 study commissioned by EE Times gathered data for three studies: an IC EDA study, this PCB study and for the first time a study on FPGA EDA tool usage. Separate summaries of the FPGA and EDA studies can be found on eeDesign.

The "2004 board study" drew 628 respondents, including 436 from North America and 192 from Europe. Fifty-five percent of respondents identified themselves as design engineers, 27 percent as engineering management, 6 percent as general management, 4 percent as layout engineer, 1 percent as CAD manager and 8 percent as "other."

Ninety percent of respondents said they are involved with PCB design while the rest are involved in layout.

Respondents said they build boards for a wide variety of applications. But the bulk of respondents create boards for: the industrial control, test and measurement market; the consumer and automotive markets; communications equipment makers; and for military and aerospace.

The study found that the average size of a PCB design team is four engineers, one more than the average in last year's study.

Seventy percent of respondents said PCB projects are completed in three months or less, 23 percent said they complete them in 4-6 months, 4 percent complete them in seven to 11 months, while 3 percent said their PCB designs take "one to three years or more to complete." The median of eight months to complete a PCB design did not change year over year.

Respondents said that 30 percent of overall design time is spent on schematic entry, 31 percent on PCB layout, 20 percent on test and manufacturing support, 11 percent on signal integrity analysis and 8 percent on "thermal/EMI analysis."

The study indicates on average there are three PCBs in each system design, with on average one FPGA and one ASIC per PCB.

North American PCB designs averaged seven layers, while European PCB designs averaged five, according to the study. Average clock speeds for designs was 125MHz, up from an average of 93MHz in 2003.

On average, 16 percent of the networks in a PCB design were considered "high-speed."

Fifty percent said they plan on engaging in the same number of PCB design starts in 2004 as they did in 2003, 20 percent said "more," 14 percent said "much more" while 7 percent indicated there will be "less" and nine percent "much less" than last year.

Forty-nine percent of PCB respondents indicated that their tool budgets will be the same in 2004 as in 2003. Twenty percent said they plan to spend more this year, and 15 percent said they plan on spending "much more" this year. Nine percent indicated they would spend less than last year on tools and 7 percent said they would spend much less on tools than they did last year.

Sixty-three percent of respondents identified signal integrity as a "very critical" issue in PCB design.

Among vendors, Agilent EEsof rated the highest in customer satisfaction with 79 percent of EEsof users surveyed indicating they were either "very" or "somewhat" satisfied with EEsof tools.

Mentor ranked second with a 75 percent approval rating followed closely by Cadence with a 71 percent satisfaction rating. The industry average was 65 percent, according to the study.

Mentor Graphics took top honors in several categories including: best after-sales support, best documentation, most ethical company, best integration with other vendors' tools, knowledgeable sales reps and best training services.

Cadence finished first as: current technology leader, technology leader in three years and clearest vision of the future, among others offers.

Meanwhile Cadence spin out OrCAD, which is now largely under the control of a distributor, also garnered several top honors, including competitive pricing, vendor familiarity, product association, purchase consideration and product usage.

- Mike Santarini

EE Times

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