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TSMC selects Atrenta as Reference Flow 5.0 partner

Posted: 10 Jun 2004 ?? ?Print Version ?Bookmark and Share

Keywords:reference flow 5.0? clock domain analysis? dft analysis? constraints analysis? automated functional analysis?

Taiwan Semiconductor Mfg Co. (TSMC) has adopted Atrenta Inc.'s low power and ERC products as key enabling technologies in the company's latest Reference Flow 5.0. Both products from Atrenta include advanced solutions for clock domain analysis, DFT analysis, constraints analysis and automated functional analysis.

TSMC also developed a chip-to-package integration flow that uses Atrenta's SpyGlass ERC, a product that validates a gate-level netlist for a wide range of electrical rules and reports critical electrical design rule violations. The tool enables chip level integration by ensuring that a high quality netlist is taken into the back-end.

Ed Wan, director of design services marketing at TSMC, said, "Incorporating these products into the power closure and the chip integration flows in Reference Flow 5.0 completes these important tasks, enabling designers to achieve faster time to market for their products."

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