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Synopsys IC, SoC tool reduces design time, cost

Posted: 15 Jun 2004 ?? ?Print Version ?Bookmark and Share

Keywords:synopsys? coreassembler? designware? nec? national semiconductor?

The new coreAssembler from Synopsys Inc. can be used to implement an IP based flow that can reduce design time, risk and cost of advanced SoC platforms and ICs.

According to Synopsys, various companies have used the design tool to efficiently create configurable, reusable platforms.

"Leading semiconductor vendors such as NEC, National Semiconductor and other companies have standardized their IP-based SoC design flows on our IP Reuse tools, including coreAssembler, and have achieved dramatic improvements in productivity," said John Chilton, SVP and GM for Synopsys' Solutions Group.

Chilton added, "Integrating larger IP-based subsystems into their designs is a growing need among DesignWare users. With the general release of coreAssembler many more companies will be able to automate the assembly of IP-based platforms, allowing designers to more efficiently build these larger subsystems for their complex SoC designs."

The coreAssembler is part of Synopsys' set of IP reuse tools, which includes coreBuilder for IP block packaging and coreConsultant for configuration and implementation of individual IP blocks. It is included for no additional charge in the DesignWare Library for use with DesignWare IP. A separately licensed version is available for $7,350 on a one-year term subscription license. The coreBuilder is priced at $88,200 on a one-year term subscription license, and the coreConsultant is licensed free-of-charge and is also included with the DesignWare Library.





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