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Transition to 90nm raising tough design issues

Posted: 15 Jun 2004 ?? ?Print Version ?Bookmark and Share

Keywords:vlsi? transistor? asic flow?

Experts delving into 90nm design and process development explored a crucial question: How will the average design team handle 90nm design?

A key question posed to experts at the Design Automation Conference here was whether 90nm design looks like any other new and immature process, or whether there will be fundamental differences from 130nm design.

Werner Goertz, vice president for VLSI business development and contract at Indian design house Wipro, said 90nm designs have so far yielded "nothing fundamentally different." He added: "It's a matter of scale. The number of transistors is huge, and there are likely significant analog blocks in the design. These factors stress a team's program management skills more than anything else."

Jonathan Fields, Agere's vice president for design platforms, added, "The backend has always had its hassles. This time there are going to be some new ones, involving memory and optional design rules in particular. But I think we are all moving forward on these."

John Martin, Chartered Semiconductor's VP for strategic alliances and partners, countered, "From the foundry side, there are substantial differences. There are some critical parameters that are very difficult to control, and we are once again introducing new materials into the interconnect stack."

IBM Corp. manager Michael Kerbaugh said design for manufacturing is much more important at 90nm. But it is not transparently embedded in tools yet. "That means the relationships between foundry people and design teams has to be deepened significantly," he said.

Alex Shubat, VP of R&D at Virage, took the measured perspective of a library developer. "The problems you first detect in one process generation always get bigger in the next-generation," he said. "It's an ongoing process. At 130nm we began to encounter things like IR drop in power lines and energy conservation. Now we have to deal with them more carefully."

Asked how a small design team would survive in a world of deepened relationships and links between applications and process development, Agere's Fields said it is seeing a major shift to ASIC flows. "The little guy is going to have a big problem taking a design to [Taiwan Semiconductor Mfg Co.] all by himself at 90nm."

Part of the problem for small design teams, Geortz added, "is disaggregation. Just as all the elements of the design flow are separating, we are needing a convergence of tools and methodology all the way from system-level to foundry. I think it's encouraging people to work with foundries to get their designs completed, or to turn to some of the new fabless ASIC houses."

Optional design rules are another troubling issue. "I'd say the design-for-manufacturing-aware flow is not quite ready yet,'' Fields said. "There is a big problem with that if the foundries consider their DFM rules to be proprietary."

- Ron Wilson

EE Times

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