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Broadcom retasks SoC for Docsis 2.0 duties

Posted: 16 Jun 2004 ?? ?Print Version ?Bookmark and Share

Keywords:soc? docsis? broadcom? cpu? mac?

Broadcom Corp. has taken a creative step toward supercharging the cable modem architecture with the introduction of the BCM3349. The cable modem chip design is a study in transition from a traditional device into what will one day be a full media gateway SoC.

The 3349 is an evolutionary step based on a previous Docsis cable modem IC, said Jay Kirchoff, director of marketing at Broadcom. The goal of the project was to turn a new version of an already complex SoC very quickly while adding the headroom to handle Docsis 2.0 throughput.

Docsis is the heart of the cable industry's move into broadband--and the foundation of its strategy to dominate the home media gateway of the future. Ver 2.0 triples the required upstream data rate to around 30Mbps, opening up a whole new realm of interactivity for cable modem users--and, more important, to media gateways. But it also creates problems for cable boxes, which are coming from a tradition of slow, user-interface-oriented CPUs that do little to touch the incoming or outgoing data streams.

The network switch industry would not be intimidated by the prospect of handling an aggregate of 70Mbps in packet traffic. But the switch industry comes with an architectural legacy of high-speed backplanes, network-processor-per-card architectures and masses of memory. Its budget for enclosures can look like the STB industry's total bill of materials.

The cable STB industry is coming from an architecturally different place. Think small embedded CPU cores handling supervisory and user interface tasks while data flows unmolested from the cable physical-layer (PHY) device through the media-access controller (MAC) and directly out to a display.

The new Broadcom chip includes upstream and downstream PHYs, a Docsis MAC, Ethernet and USB controllers, an SDRAM interface, an enhancement-bus interface and a CPU core. In that regard it is much like its predecessor.

But the Broadcom designers worked under the hood to get the performance up. The first step was to develop an enhanced MAC. Broadcom is holding the exact design of the access controller close to its collective chest, but Kirchoff said there were specific hardware changes to accommodate the efficient blending of data, streaming media and voice, as allowed under Docsis 2.0 and as envisioned for media gateway applications.

Core instructions

The CPU also came in for attention. The design team reworked the CPU core's interfaces to the MAC on one side and the expansion-bus interface on the other side. That by itself saved instruction cycles, which translates directly into throughput. Of course, the designers also increased the clock frequency of the MIPS core, further boosting packet-processing speed.

But the big gain came from use of the MIPS CorExtend capability to add instructions to the MIPS core specifically for packet processing. By reducing the number of instruction cycles necessary in critical inner loops, the added instructions had a positive effect on both packet throughput and, more than likely, power efficiency, Broadcom said.

This tight focus on the packet data path allowed the Broadcom designers to reuse a great deal of intellectual property from the previous modem SoC. That, in turn, allowed a very fast design cycle. Kirchoff said that the design occupied "the better part of 2003" - less than a year for a significant SoC. Just as important, in this era when designs can die in the never-never land of respins, the chip went from first samples to production quickly, he said.

The chip and its software are now certified as a Docsis 2.0 data modem, and the company said that customers are rapidly taking it into the media gateway applications space the designers envisioned. The chip is available now for $20 each in lots of 10,000.

- Ron Wilson

EE Times

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