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SOI mobility harmed by scattering, Toshiba researchers report

Posted: 17 Jun 2004 ?? ?Print Version ?Bookmark and Share

Keywords:cmos devices? silicon-on-insulator? transistors? lsi? ieee 2004?

As silicon-on-insulator CMOS devices shrink into the ultra-thin body range, carrier mobility in fully depleted silicon-on-insulator transistors is affected adversely by scattering effects, a team of researchers based at Toshiba Corp. reported here at the IEEE 2004 Silicon Nanoelectronics Workshop.

Ken Uchida, a staff researcher at Toshiba's advanced LSI laboratory in Yokohama, Japan, said as the silicon layer in SOI devices is thinned to below 20nm, carrier mobility is slowed by acoustic phonon scattering, a phenomenon related to vibrations in the silicon lattice in ultra-thin body devices.

Besides phonon scattering, carriers (electrons and holes) are affected by surface roughness, as well as Coulomb scattering related to the tendency of electrons to repel each other. Phonon scattering is the major cause of the mobility degradation, Uchida said. The Toshiba researchers studied devices at 25K, and found that phonon scattering was suppressed in the super-cooled devices, an indication that phonon scattering is the "dominant mechanism" of mobility degradation.

Shin-ichi Takagi, who recently moved from Toshiba to a new job as a University of Tokyo professor, worked with Uchida and Junji Koga on the research. Generally, fully depleted SOI devices require a silicon thickness that is about one-third to one-fourth the gate length. A 5nm SOI thickness would be required for a transistor with a 15- to 20nm gate length. Creating wafers with such a thin silicon thickness, with minimal surface roughness, will present a major challenge as fully depleted SOI moves into manufacturing over the next decade, Takagi said.

Multigate devices, such as FinFETs, are all targeted at fully depleted SOI structures, he noted, so the scattering phenomena could become important in the next decade, beyond the 45nm node.

The mobility degradation in ultra-thin body SOI devices is larger in devices with lower gate voltages, he said.

There is a silver lining in the Toshiba study: The researchers managed to thin the silicon thickness to 3- to 5nm in thickness. At this range, the experimental results confirmed a mobility improvement that has long been predicted by theory. In the 3- to 5nm range, electron transport moves from quantum energy states called "four-fold valleys" to "two-fold valleys," which increases the carrier transport mass and improves the mobility.

However, the improvement seen experimentally was less than expected. "From 3.5- to 4.5nm, the enhancement is very small experimentally compared with what has been predicted in simulations," said Uchida, who is currently a visiting scholar at Stanford University. He postulated that there may be other scattering mechanisms, beyond phonon scattering, that impair carrier mobility in the 3- to 5nm range.

Besides scattering in the silicon layer, mobility also is affected by scattering mechanisms in the high-k oxides, such as hafnium oxide, Takagi said. "Researchers such as Max Fischetti at IBM have shown that there is a lower phonon energy in the high-k oxides that will have an impact on mobilities. That may cause the industry to look for high-k materials that have higher permittivity and higher phonon energies," Takagi said.

The workshop, held June 13-14 prior to the Symposium on VLSI Technology, is blossoming into an important conference in its own rights, said David Frank, the IBM researcher who chaired the nanoelectronics workshop. About 160 engineers attended the ninth meeting of the workshop. The conference is focused on exploratory nonscale MOSFETs, alternate field effect transistors, single electron devices and nanoscale memory types.

- David Lammers

EE Times

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