Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
EE Times-Asia > EDA/IP

Cadence promises full SystemVerilog support

Posted: 18 Jun 2004 ?? ?Print Version ?Bookmark and Share

Keywords:systemverilog? eda? hardware? software?

As twenty-six EDA vendors presented their plans for SystemVerilog support at the Design Automation Conference last week, Cadence Design Systems was notably missing. But Cadence, which missed a materials submission deadline for last week's Accellera event, plans to support the full SystemVerilog language, representatives say.

At Accellera's SystemVerilog "Right here, right now" event, a parade of EDA vendors set forth their product plans for SystemVerilog, along with IP providers and training firms. Cadence's absence led some to wonder whether the EDA giant plans to support the language, but there's no need for concern, said Victor Berman, group director for Cadence's language and standards strategy.

"We were writing Verilog even before it existed," said Berman, noting that it would be odd if Cadence did not support the evolution of the language it helped proliferate to the market. "We're going to support the whole language. That's been our goal from day one."

Berman noted that many tools in Cadence' verification flow already support certain parts of SystemVerilog, and he said a fourth quarter release of Incisive and Encounter will have greater SystemVerilog support in synthesis, formal verification, emulation and simulation.

"We'll have a big chunk of this work done in Q4 for the design subset of SystemVerilog and for the assertions," said Berman. "We'll be covering most of that in the RTL Compiler synthesis tool, in formal verification, and some in emulation, stretching into 2005."

Berman said Cadence is making a concerted effort to ensure it offers SystemVerilog across the entire flow "in a synchronized way," as all the design and verification tools work together and are somewhat interrelated.

Cadence Incisive platform marketing VP George Zafiropoulos said Cadence sees SystemC as a complimentary language to SystemVerilog. He noted that SystemC is building momentum as a system-on-chip architecture modeling language, testbench language, and more immediately, a verification language for hardware and software.

- Mike Santarini

EE Times

Article Comments - Cadence promises full SystemVerilog ...
*? You can enter [0] more charecters.
*Verify code:


Visit Asia Webinars to learn about the latest in technology and get practical design tips.

Back to Top