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TI outlines new options for chip scaling

Posted: 18 Jun 2004 ?? ?Print Version ?Bookmark and Share

Keywords:embedded sram? microprocessor? transistor? sige?

Texas Instruments Inc. (TI) revealed that its semiconductor research teams have developed cost effective techniques to lower chip power consumption, and a new approach to increase overall performance.

The company says the new power management technologies can reduce leakage power from idle transistors by a factor of 1,000, while unique strained silicon techniques can increase transistor performance by 35 percent. TI plans to offer extremely dense embedded SRAM with its 65nm process, with the six transistors in a cell occupying less than half a square micron of area and 1.57Mb fitting in a square millimeter. An extremely small SRAM cell allows the company to integrate very large amounts of memory close to its processor cores, accelerating application execution.

To continue improvements in transistor performance for its microprocessor-class products, the company is pursuing strained silicon as a way to increase drive current, a primary factor in transistor switching speed, which in turn determines processor operating speed. The semiconductor industry has explored a number of different techniques to increase current flow by introducing regions enriched with germanium atoms to strain the silicon and make it easier for electrons to move. TI believes it is using the smallest amount of SiGe in the industry and placing it much closer to the transistor channel than previously demonstrated to achieve the maximum strain with the fewest defects.

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