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Chip melds TCP, RDMA for Ethernet

Posted: 18 Jun 2004 ?? ?Print Version ?Bookmark and Share

Keywords:siliquent technologies? ethernet processor? advanced ethernet processor? ethernet? lan?

Siliquent Technologies Inc. is sampling a single-chip Ethernet processor that can handle TCP offload duties and RDMA operations. The 10Gbps Advanced Ethernet Processor is intended for complex packet forwarding when Ethernet takes on LAN, cluster-interconnect and storage duties.

Siliquent's chief executive, Charles Chi, said four groups of competitors help to validate the bottlenecks Ethernet creates when it's used as a serial interconnect. Traditional developers of Ethernet media-access control devices, like Broadcom Corp., are trying to develop "monster MACs" that include TCP offload and RDMA functions, but are limited to 1Gbps rates, Chi said. Specialized producers of TCP offload and oversubscription engines, including Intel Corp. and Ample Communications, have good hardware engines but their scope is too limited, he said.

At the system level, a few startups such as Chelsio Communications Inc. have designed their own ASICs for insertion into PCI-X cards for servers. Finally, Packet Design spin-off Precision I/O Inc. claims that TCP and RDMA problems can be handled with only software adjuncts to network interface cards.

Chi said most OEM customers see standard packet processors as the way to go, if power dissipation is kept down. Microcoded engines were seen as the proper trade-off between programmable processors and hardwired state machines. Siliquent marketing VP Debbie Vogt said that microcoded blocks also make customers feel safer in dealing with hardware acceleration of TCP functions.

The design was seen as necessary in next-generation servers, because traditional Ethernet network interface cards tend to overload host CPUs with memory requests. The Siliquent AEP has its own RISC-based host core, and the resulting "intelligent NIC" can place its own data into host memory.

While storage applications will be based on iSCSI and iWARP protocols, the chipset can use the installed base of Infiniband and Fibre Channel application programming interfaces and "verbs," so existing server and storage applications can be run unchanged.

The AEP chip can interface to the server system through a PCI-X, SPI or PCI Express interface. Data is passed through an upper-layer-processing (ULP) transmitter, a TCP transmitter and a framer, which performs segmentation and reassembly of data. Data exported to the network uses a SPI-4 interface. Incoming data from the network passes through a classifier and lookup engine, then through a TCP receiver and ULP receiver. Because a lookup engine and classifier are integrated into the design, special devices, such as ternary CAMs, are unnecessary, and the chip can use standard SDRAM interfaces.

Siliquent will disclose prices, pinouts and production schedules when the chip reaches general sampling this summer, but Chi said the design is past simulation or netlist stage. A few customers have prototypes in hand, he said, and have validated the 10Gbps wire speed throughput of the packet parser.

"This can be packaged to design a multiport 1Gb NIC or a single-port 10Gb NIC," Chi said. "The 10Gb benchmark was important to hit, but we wanted to give customers flexibility on when to upgrade to 10Gb Ethernet."

With roots in Mountain View, Calif., and Tel Aviv, Israel, Siliquent has received initial angel funding from Israeli telecom OEM Orckit Systems. Chi, general partner at Greylock Partners, recently joined as chief executive.

- Loring Wirbel

EE Times

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