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Cypress rolls out fast PLL clock drivers for DIMMs

Posted: 21 Jun 2004 ?? ?Print Version ?Bookmark and Share

Keywords:cypress semiconductor? cy2sstv857-32? phase-locked loop clock driver? pll clock driver? dual inline memory module?

Cypress Semiconductor Corp. disclosed that it is now sampling one of the industry's fastest phase-locked loop (PLL) clock drivers for registered dual inline memory modules (DIMMs).

Operating at clock frequencies up to 230MHz, the CY2SSTV857-32 exceeds the JEDEC specification for the DDR400 standard. It is a low-skew, low-jitter zero-delay buffer (ZDB) designed to distribute differential clocks in high-speed DIMMs in applications such as servers, workstations, routers and switches.

According to the company, the new device has very low clock skew and jitter characteristics, ensuring clock signal integrity and superior reliability. "The CY2SSTV857-32 is the ideal clock driver solution for high performance DIMMs that transfer multiple gigabytes of data per second," said Rob Raghavan, senior product marketing manager for Cypress's Timing Technology Division.

The PLL clock driver generates ten differential pair clock outputs from one differential pair clock input. It also features differential feedback clock outputs and inputs, enabling it to serve as a ZDB. When used as a ZDB in nested clock trees, the CY2SSTV857-32 locks unto the input reference and translates it with near-zero delay to low-skew outputs.

Available in both commercial and full-industrial temperature ranges, the CY2SSTV857-32 is housed in 48-pin TSSOP and 40-pin MLF/QFN.

For more information, visit the Cypress website.

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