Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
?
EE Times-Asia > EDA/IP
?
?
EDA/IP??

IEEE unifies Verilog standards efforts

Posted: 29 Jun 2004 ?? ?Print Version ?Bookmark and Share

Keywords:verilog? ieee 1364? systemverilog? ieee?

Putting to rest fears of a Verilog language schism, the IEEE has decided to form a single working group that will encompass both SystemVerilog and the further evolution of the IEEE 1364 Verilog language standard.

The move follows criticisms of Accellera's decision to take SystemVerilog to a new IEEE working group rather than the existing 1364 committee.

In May, Accellera voted to take SystemVerilog to a new working group under the IEEE Corporate Advisory Group (CAG), rather than IEEE 1364, which resides under the Design Automation Standards Committee (DASC). While Accellera said CAG voting rules would permit faster standardization, critics feared that SystemVerilog, designated as the IEEE p1800 project, would diverge from the IEEE 1364-2001 language standard upon which it was supposed to be built.

To resolve those fears, the IEEE has decided to form a new working group under both CAG and DASC sponsorship, and to bring both p1800 and IEEE 1364 into this working group. Thus, 1364 will be a project (p1364), but not a separate working group. The as yet unnamed working group will have the "entity" voting rule - that is, one company, one vote - that attracted Accellera to the CAG initially.

"Peace has broken out in Verilog land," declared Dennis Brophy, Accellera chairman. "Accellera knew from the beginning that the CAG would work with current society sponsors, and is delighted with the accord that has been reached. The IEEE process works."

Mike McNamara, chair of the IEEE 1364 working group, was very critical of Accellera's decision to take SystemVerilog to a new IEEE working group. But he supports the latest IEEE moves, and he seconded the motion before the DASC to create one working group with dual sponsorship.

"We asked for SystemVerilog to come to 1364 last year, and it didn't happen," McNamara said. "If the mountain won't come to Mohammed, Mohammed should come to the mountain. If we can take 1364 and put it in with 1800 and get a unified standard, I'm totally fine with that."

"I'm really pleased with the flexibility the DASC has shown," said Ed Rashba, manager of new technical programs for the IEEE. "Their willingness to partner with the CAG and adopt the entity approach is certainly going to help attract new projects in the future."

The agreement will help accelerate SystemVerilog standardization, Rashba said. "We're hoping the standard will be complete in 2005," he said.

The proposal for a single working group was approved at a DASC steering committee meeting June 11, noted Peter Ashenden, DASC chair. CAG and Accellera officers agreed to the proposal last week, and a joint sponsorship committee was formed. On Wednesday, June 23, 2004, the IEEE-SA NesCom committee approved the p1800 project, paving the way for the new working group to start operating.

"There has been strong good will among DASC, CAG and Accellera participants, with a focus on finding a way to satisfy all concerns," Ashenden said. "The joint sponsorship agreement between DASC and CAG will allow us to bring to bear both DASC's experience in EDA standards projects and CAG's support for corporate interests."

The new working group will have its first meeting July 1 in Frankfurt, Germany. Intel's Johny Srouji is the initial chair, and the group will hold nominations and balloting for officers.

The question now is what the p1364 project will entail. The 1364 working group had begun work on Verilog 2005, which was mostly derived from SystemVerilog, but the scope of that project is being amended, noted both Rashba and McNamara.

"As far as I understand, p1800 takes SystemVerilog 3.1a pretty much as is, and makes a standard that lives on top of 1364-2001," McNamara said.

"1364 will continue its efforts, clarifying any ambiguities in the existing standard. I think 1364 can begin the work of merging SystemVerilog extensions into the base language, so we can have one LRM [language reference manual] in a few years. But it's up to the working group to decide."

Karen Bartleson, director of interoperability at Synopsys, explains Accellera's reasons for donating SystemVerilog to the IEEE CAG in an EDA Views column located at EEdesign, and notes that the new IEEE decision will result in a unified standard.

- Richard Goering

EE Times





Article Comments - IEEE unifies Verilog standards effor...
Comments:??
*? You can enter [0] more charecters.
*Verify code:
?
?
Webinars

Seminars

Visit Asia Webinars to learn about the latest in technology and get practical design tips.

?
?
Back to Top